This PDF file contains the front matter associated with SPIE Proceedings Volume 8683, including the Title Page, Copyright Information, Table of Contents, Introduction and Conference Committee listing.

EUV insertion timing for High Volume Manufacturing is still an uncertainty due to source power and EUV mask infrastructure limitations. Directed Self Assembly (DSA) processes offer the promise of providing alternative ways to extend optical lithography cost-effectively for use in the 10nm node and beyond. The goal of this paper is to look into the technical prospect of DSA technology, particularly in the computational and DFM area. We have developed a prototype computational patterning toolset in-house to enable an early Design –Technology Co-Optimization to study the feasibility of using DSA in patterning semiconductor devices and circuits. From this toolset we can identify the set of DSA specific design restrictions specific to a DSA process and plan to develop a novel full chip capable computational patterning solution with DSA. We discuss the DSA Computational Lithography (CL) infrastructure using the via and fin layers as examples. Early wafer data is collected from the DSA testmask that was built using these new toolsets. Finally we discuss the DSA ecosystem requirements for enabling DSA lithography and propose how EDA vendors can play a role in making DSA Lithography (DSAL) a full-chip viable technology for multiple process layers.

The CMOS logic 22nm node is being done with single patterning and a highly regular layout style using Gridded Design Rules (GDR). Smaller nodes will require the same regular layout style but with multiple patterning for critical layers. A “lines and cuts” approach is being used to achieve good pattern fidelity and process margin, with extendibility to ~7nm.[1] In previous work, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective down to the 16nm node.[2,3,4,5] The transition from single- to double- and in some cases triple- patterning was evaluated for different layout styles, with highly regular layouts delaying the need for multiple-patterning compared to complex layouts. To address mask complexity and cost, OPC for the “cut” patterns was studied and relatively simple OPC was found to provide good quality metrics such as MEEF and DOF.[6,7] This is significant since mask data volumes of <500GB per layer are projected for pixelated masks created by complex OPC or inverse lithography; writing times for such masks are nearly prohibitive. In this study, we extend the scaling using SMO with simplified OPC in a technique called “SMOLite” beyond 16nm. The same “cut” pattern is used for each set of simulations, with “x” and “y” locations for the cuts scaled for each node. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops. Another approach for scaling the “cut” pattern has also been studied. This involves the use of a hole pitch division process to create a grid template combined with a relatively large “selection” pattern to create cuts at the desired grid locations. Experimental demonstration of the cut approach using SMO-Lite and a grid template will be presented. Wafer results have been obtained at a line half-pitch of 20nm, which corresponds to the gate pitch at the 10nm node.

For the 14nm node and beyond there are many integration strategy decisions that need to be made. All of these can have a significant impact on both alignment and overlay capability and need to be carefully considered from this perspective. One example of this is whether a Litho Etch Litho Etch (LELE) or a Self Aligned Double Patterning (SADP) process is chosen. The latter significantly impacting alignment and overlay mark design. In this work we look at overlay performance for a Back End of Line (BEOL) SADP Dual Damascene (DD) process for the 14nm node. We discuss alignment mark design, particularly focusing on the added complexity and issues involved in using such a process, for example design of the marks in the Metal Core and Keep layers and recommend an alignment scheme for such an integration strategy.

Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models, which must balance accuracy demands with simulation runtime boundary conditions, rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. While certain system input variables, such as scanner numerical aperture, can be empirically tuned to wafer CD data over a small range around the presumed set point, it can be dangerous to do so since CD errors can alias across multiple input variables. Therefore, many input variables for simulation are based upon designed or recipe-requested values or independent measurements. It is known, however, that certain measurement methodologies, while precise, can have significant inaccuracies. Additionally, there are known errors associated with the representation of certain system parameters. With shrinking total CD control budgets, appropriate accounting for all sources of error becomes more important, and the cumulative consequence of input errors to the computational lithography model can become significant. In this work, we examine with a simulation sensitivity study, the impact of errors in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD Bias values are based on state of the art mask manufacturing data and other variables changes are speculated, highlighting the need for improved metrology and awareness.

Lithographers had hoped that single patterning would be enabled at the 20nm node by way of EUV lithography. However, due to delays in EUV readiness, double patterning with 193i lithography is currently relied upon for volume production for the 20nm node’s metal 1 layer. At the 14nm and likely at the 10nm node, LE-LE-LE triple patterning technology (TPT) is one of the favored options [1,2] for patterning local interconnect and Metal 1 layers. While previous research has focused on TPT for contact mask, metal layers offer new challenges and opportunities, in particular the ability to decompose design polygons across more than one mask. The extra flexibility offered by the third mask and ability to leverage polygon stitching both serve to improve compliance. However, ensuring TPT compliance – the task of finding a 3-color mask decomposition for a design – is still a difficult task. Moreover, scalability concerns multiply the difficulty of triple patterning decomposition which is an NP-complete problem. Indeed previous work shows that network sizes above a few thousand nodes or polygons start to take significantly longer times to compute [3], making full chip decomposition for arbitrary layouts impractical. In practice Metal 1 layouts can be considered as two separate problem domains, namely: decomposition of standard cells and decomposition of IP blocks. Standard cells typically include only a few 10’s of polygons and should be amenable to fast decomposition. Successive design iterations should resolve compliance issues and improve packing density. Density improvements are multiplied repeatedly as standard cells are placed multiple times. IP blocks, on the other hand, may involve very large networks. This paper evaluates multiple approaches to triple patterning decomposition for the Metal 1 layer. The benefits of polygon stitching, in particular, the ability to resolve commonly encountered non-compliant layout configurations and improve packing density, are weighed against the increased difficulty in finding an optimized, legal decomposition and coping with the increased scalability challenges.

A robust source mask optimization (RSMO) methodology has been developed for the first time to decrease variations of critical dimension (CD) and overlay displacement on wafer caused by extremely complex exposure tools and mask patterns. The RSMO methodology takes into account exposure tool variations of source shape, aberrations and mask as well as dose and focus to get source shapes and mask patterns robust to the exposure tool variations. A comparison between the conventional SMO and the new RSMO found that the RSMO improved the edge placement error (EPE) and displacement sensitivity to coma and astigmatism aberrations by 14% and 40%, respectively. Interestingly, even a greatly-simplified source from the RSMO provides totally smaller EPE than uselessly complex source shape from the conventional SMO. Thus, the RSMO methodology is much more effective for semiconductor products with high volume production.

The k1 factor continues to be driven downward in ArF immersion lithography, even below its limit from optical theory, using various lithographic techniques such as combination of Source and Mask Optimization (SMO) and multiple patterning. Such a low k1 factor tends to lead to extremely high sensitivity tp imaging parameters such as aberrations, distortion, illumination pupilgram shape, dose, focus, etc. Therefore, fast, precise and stable settings of these parameters are crucial to make such hyper low k1 lithography practical. We introduce various kinds of imaging application tools and technique, which we have been developing, to support the imaging parameter settings and control. The application tools cover illumination pupilgram adjustment for freeform illumination, automatic aberration control, and thermal aberration parameter settings.

Mask-induced aberration, which causes the deterioration of pattern fidelity owing to the phase difference between the diffraction orders in sub-wavelength lithography conditions, is an intricate problem. To evaluate the extent of the effect computationally, a rigorous electromagnetic field solver is applied. Reduction in the computation time of full-3D calculation is desirable in order to calculate practical patterns of mask layout in short period of time. We propose a new approach based on the Constrained Interpolation Profile (CIP) scheme with Method of Characteristics (MoC) to achieve the reduction of computation time. The CIP scheme is characterized by high accuracy to maintain the phase of each propagating wave using spatial derivatives. Constrained interpolation with derivatives is efficient for reducing the number of cells in the spatial domain because the requirement for keeping the phase accuracy of wavefront is relaxed. Non-uniform meshing also reduces the amount of computation time. The CIP scheme connects the mask topography simulation using non-uniform mesh to the traditional imaging algorithm smoothly. In this paper, we discuss the accuracy of CIP-based Mask3D simulation and the applicability to lithography issues.

More complex source and mask shapes are required to maximize the process window in low κ₁ era. In simulation, the improvement can be shown well with ideal source and mask shapes. However imperfection of the source and mask can cause critical dimension (CD) errors and results in smaller process margin than expected one. In this paper, it is shown that how process margins can be improved with different source and mask complexities. Also the effect of source and mask complexities on CD errors and process margin degradation is discussed. The error source of the electron beam mask pattern generator is investigated and used for mask CD uniformity estimation with different mask complexity.

Nikon’s Intelligent Illuminator, a freeform pupilgram generator, realizes a high flexibility for pupilgram control by using more than 10,000 degrees-of-freedom for pupilgram adjustment. In this work, an Intelligent Illuminator was integrated into an ArF scanner, the Nikon NSR-S621D. We demonstrate the pupilgram setting accuracy by direct correlation between on-body measured pupilgram and desired target pupilgram. We show that the Intelligent Illuminator is used for fine tuning of the pupilgram to match optical proximity effect (OPE) characteristics. We experimentally confirmed that a global source optimization software realized an improvement of lithographic process window without changing OPE characteristics by using optimized pupilgram made by Intelligent Illuminator.

Resolution Enhancement Techniques have continuously improved over the last decade, driven by the ever growing constraints of lithography process. Despite the large number of RET applied, some hotspot configurations remain challenging for advanced nodes due to aggressive design rules. Inverse Lithography Technique (ILT) is evaluated here as a substitute to the dense OPC baseline. Indeed ILT has been known for several years for its near-to-ideal mask quality, while also being potentially more time consuming in terms of OPC run and mask processing. We chose to evaluate Mentor Graphics’ ILT engine “pxOPC^TM” on both lines and via hotspot configurations. These hotspots were extracted from real 28nm test cases where the dense OPC solution is not satisfactory. For both layer types, the reference OPC consists of a dense OPC engine coupled to rule-based and/or model-based assist generation method. The same CM1 model is used for the reference and the ILT OPC. ILT quality improvement is presented through Optical Rule Check (ORC) results with various adequate detectors. Several mask manufacturing rule constraints (MRC) are considered for the ILT solution and their impact on process ability is checked after mask processing. A hybrid OPC approach allowing localized ILT usage is presented in order to optimize both quality and runtime. A real mask is prepared and fabricated with this method. Finally, results analyzed on silicon are presented to compare localized ILT to reference dense OPC.

Traditional rule-based and model-based OPC methods only simulate in a very local area (generally less than 1um) to identify and correct for systematic optical or process problems. Despite this limitation, however, these methods have been very successful for many technology generations and have been a major reason for the industry being able to tremendously push down lithographic K1. This is also enabled by overall good across-exposure field lithographic process control which has been able to minimize longer range effects across the field. Now, however, the situation has now become more complex. The lithographic single exposure resolution limit with 1.35NA tools remains about 80nm pitch but the final wafer dimensions and final wafer pitches required in advanced technologies continue to scale down. This is putting severe strain on lithographic process and OPC CD control. Therefore, formerly less important 2nd order effects are now starting to have significant CD control impact if not corrected for. In this paper, we provide examples and discussion of how optical and chemical flare related effects are becoming more problematic, especially at the boundaries of large, dense memory arrays. We then introduce a practical correction method for these systematic effects which reuses some of the recent long range effect correcting OPC techniques developed for EUV pattern correction (such as EUV flare). We next provide analysis of the benefits of these OPC methods for chemical flare issues in 193nm lithography very low K1 lithography. Finally, we summarize our work and briefly mention possible future extensions.

As semiconductor nanolithography is pushed to smaller dimensions, process yields can suffer from three dimensional sub-wavelength imaging effects. Mask topography can influence the propagating diffracted field causing errors such as pitch dependent defocus and degraded useable depth of focus (UDOF). In this work, the compensation of diffracted phase error is realized through the manipulation of the wavefront in the projection lens pupil. Mask exposure data is presented showing how such manipulation can increase the UDOF for several mask structure types, leading to UDOF improvement between 18% and 83%. An analytical model is presented to understand trends seen in experimental data through pitch. Results also show that an asymmetric wavefront can be tuned to particular geometries, providing a UDOF improvement for line ends under restricted processing conditions.

Traditional SRAF placement has been governed by a generation of rules that are experimentally derived based on measurements on test patterns for various exposure conditions. But with the shrinking technology nodes, there are increased challenges in coming up with these rules. Model-based SRAF placement can help in improved overall process window, with less effort. This is true especially for two-dimensional layouts, where SRAF placement conflicts can provide a formidable challenge with varying patterns and sources. This paper investigates the trade-offs and benefits of using model-based SRAF placement over rule-based for various design configurations on a full chip. The impact on cost, time, process-window and performance will be studied. This paper will also explore the benefits and limitations of more complex free-form SRAF and OPC shapes generated by Inverse Lithography Technology (ILT), and strategies for integration into a manufacturable mask.

Reflection by wafer topography and underlying layers during optical lithography can cause unwanted exposure in the resist [1]. This wafer stack effect phenomenon which is neglected for larger nodes than 45nm, is becoming problematic for 32nm technology node and below at the ionic implantation process. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but increases process complexity and adds cost and cycle time penalty. As a consequence, an OPC based solution is today under evaluation to cope with stack effects involved in ionic implantation patterning [2] [3]. For the source drain (SD) ionic implantation process step on 28nm Fully Depleted Silicon-on-Insulator (FDSOI) technology, active silicon areas, poly silicon patterns, Shallow Trench Isolation (STI), Silicon-on-Insulator (SOI) areas and the transitions between these different regions result in significant SD implant pattern critical dimension variations. The large number of stack variations involved in these effects implies a complex modeling to simulate pattern degradations. This paper deals with the characterization of stack effects on 28nm node using SOI substrates. The large number of measurements allows to highlight all individual and combined stack effects. A new modeling flow has been developed in order to generate wafer stack aware OPC model. The accuracy and the prediction of the model is presented in this paper.

Printing small vias with tight pitches is becoming very challenging and consequently, different techniques are explored to achieve a robust and stable process. These techniques include reverse tone imaging (RTI) process, source optimization, mask transmission (attenuated Phase Shift Masks (attnPSM) versus binary thin OMOG masks), three-dimensional mask effects models, and SRAF printing models. Simulations of NILS, MEEF, DoF and process variability (PV) band width across a wide range of patterns are used to compare these different techniques in addition to the experimental process window. The results show that the most significant benefits can be gained by using attnPSM masks in conjunction with source optimization and RTI process. However, this improvement alone is not enough; every facet of the computational lithography and process must be finely tuned to produce sufficient imaging quality. As technology continues to shrink, Electromagnetic Field (EMF)-induced errors limit the scalability of this process and we will discuss the need for advanced techniques to suppress and correct for them.

Source Mask Optimization (SMO) has become an integral part of resolution enhancement techniques (RET) for almost all critical layers at advanced technology nodes. Over the past couple of years, various flows have emerged for integrating SMO into mainstream RET selection. These flows revolve mainly around clip selection, resist model, verification and analysis metrics, design rule optimization, and so on. There has also been strong emphasis on the quality of mask that is conjugated for source selection process. All these variations in analysis and rigorous simulations for flow selection are critical but they also create a bottleneck in overall RET development. In this paper, we demonstrate an initial RET development flow for 20 nm technology with emphasis on quantifying benefits coming from source and mask. We also report challenges that are encountered in the foundry environment when moving from RET development to production. In conclusion, we demonstrate a reliable solution that could be integrated early in RET development and easily adapted for a production environment.

The computational lithography such as inverse lithography technique (ILT) or source mask optimization (SMO) is considered as the necessary technique for the extremely low k1 lithography process of sub-20nm node. The ideal curvilinear mask design for computational lithography gives the impacts and requires many changes on the photomask fabrication from mask data preparation to measurement and inspection. In this paper, we present the current status and new requirements for the computational lithography mask in viewpoint of the manufacturability for mass production. The manufacturability of computational lithography mask can be realized by the predictable and manageable patterning quality. Here, we have proposed new data flow for ILT which covers what the preferred target design is for ILT, new verification method, required mask model accuracy, and resolution improvement method. Furthermore, considering acceptable writing time (<24 hours) and computation limit on convolution, the current ILT technique is shown to have the limit of application area.

Source mask optimization (SMO) is widely used to make state-of-the-art semiconductor devices in high volume manufacturing. To realize mature SMO solutions in production, the Intelligent Illuminator, which is an illumination system on Nikon scanner, is useful because it can provide generation of freeform sources with high fidelity to the target. Proteus SMO, which employs co-optimization method and an insertion of validation with mask 3D effect and resist properties for an accurate prediction of wafer printing, can take into account the properties of Intelligent Illuminator. We investigate an impact of the source properties on the SMO to pattern of a static-random access memory. Quality of a source made on the scanner compared to the SMO target is evaluated with in-situ measurement and aerial image simulation using its measurement data. Furthermore we discuss an evaluation of a universality of the source to use it in multiple scanners with a validation with estimated value of scanner errors.

A new optical metric, termed resist deformation factor (RDF), to represent deformation of three-dimensional (3D) resist profile has been introduced into a source and mask optimization (SMO) flow to mitigate defects caused by a reactive ion etching (RIE) process at the lithography stage. Under the low-k₁ lithography conditions with both a highly-coherent source and a complicated mask, the 3D resist profile is subject to top-loss or bottom footing, resulting in hotspots and/or defects after the RIE process. In order to represent the 3D resist profile on a fast lithography simulation, a sliced latent image along resist depth direction is used to define RDF as the ratio of integrated optical intensities within the resist pattern to those around its surrounding area. Then the SMO flow incorporating the RDF into its cost function is implemented to determine both a source and a mask as the 3D resist profile is less likely to deform. The result of new SMO flow with RDF shows 30% improvement of resist top-loss.

This work describes freeform source optimization considering mask error enhancement factor (MEEF), optical proximity effect (OPE), process window, and hardware-specific constraints. Our algorithm allows users to define maximum allowed MEEF and OPE error as constraints without defining weights among the metrics. We also consider hardware specific constraints, so that the optimized source is suitable to be realized in Nikon’s Intelligent Illumination hardware. Our approach utilizes a global optimization procedure to arrive at a freeform source shape solution, and since each source grid-point is assigned as variable, the source solution encompasses the maximum amount of degrees of freedom.

The overlay, CDU and focus requirements for the 20nm node can only be met using a holistic lithography approach whereby full use is made of high-order, field-by-field, scanner correction capabilities. An essential element in this approach is a fast, precise and accurate in-line metrology sensor, capable to measure on product. The capabilities of the metrology sensor as well as the impact on overlay, CD and focus will be shared in this paper.

Current technology nodes, as well as subsequent generations necessitate ongoing improvements to the mix-and-match overlay (MMO) capabilities of lithography scanners. This work will introduce newly developed scanner solutions to address this requirement, and performance data from the latest generation immersion scanner, the NSR-S622D, will be introduced. Enhanced MMO accuracy is imperative for the 22 nm half-pitch and future technology nodes. In order for the matched overlay accuracy to approach single machine overlay (SMO) capabilities, MMO errors must be reduced further. The dominant MMO error sources can be divided into three main areas: SMO, lens distortion matching and wafer grid matching. Nikon continues to decrease these matching error contributors over time, and the latest generation NSRS622D immersion scanner provides a number of innovative solutions to satisfy the most demanding overlay matching requirements ; as a result MMO performance within 3nm is achieved on S622D. Moreover, overlay master system is developed for further product overlay accuracy and stability improvement.

When the technology node of logic devices is sub-14nm, finding lithographic solutions for most of the critical layers is challenging. For instance, metal 1 interconnect layer is one of the most lithographically difficult layers in a logic design, not only owing to its two-dimensional topology with irregular geometric shapes but also owing to the small minimum pitches in two orientations. A double pattern technology with 193nm immersion is insufficient to resolve the critical features at the minimum pitch. Only 23% cell shrinkage, with respect to a 16/14nm-node design, is predicted by examining most of the crucial lithographic metrics. To archive an expected cell shrinkage of approximately 50% for the next node, immersion technology with more than a double split pitch, such as triple patterning technology, appears to be able to drive the minimum pitch to satisfy sub-14nm-node lithographic requirements; however, process complexity and cost are unavoidably higher. Analyses herein of the lithographic metrics reveal that a common process window and CD uniformity do not fully suffice for the lithographic process. The main cause of this failure is a very large best focus shift among the critical features due to the 3D mask effect. Reducing the wavelength of the light source to 13.5nm in the extreme ultraviolet range dramatically improves image resolution, the process window and the CD uniformity even with traditional illumination source shapes. Selection of lithographic solution for each critical layer is relevant, considering image performance, design style and constraints, process integration, running cost, and other factors.

Reducing lithography pattern variability has become a critical enabler of ArF immersion scaling and is required to ensure consistent lithography process yield for sub-30nm device technologies. As DUV multi-patterning requirements continue to shrink, it is imperative that all sources of lithography variability are controlled throughout the product life-cycle, from technology development to high volume manufacturing. Recent developments of new ArF light-source metrology and monitoring capabilities have been introduced in order to improve lithography patterning control.^[1] These technologies enable performance monitoring of new light-source properties, relating to illumination stability, and enable new reporting and analysis of in-line performance.

Thermal aberration becomes a serious problem in the production of semiconductors for which low-k1 immersion lithography with a strong off-axis illumination, such as dipole setting, is used. The illumination setting localizes energy of the light in the projection lens, bringing about localized temperature rise. The temperature change varies lens refractive index and thus generates aberrations. The phenomenon is called thermal aberration. For realizing manufacturability of fine patterns with high productivity, thermal aberration control is important. Since heating areas in the projection lens are determined by source shape and distribution of diffracted light by a mask, the diffracted pupilgram convolving illumination source shape with diffraction distribution can be calculated using mask layout data for the thermal aberration prediction. Thermal aberration is calculated as a function of accumulated irradiation power. We have evaluated the thermal aberration computational prediction and control technology “Thermal Aberration Optimizer” (ThAO) on a Nikon immersion system. The thermal aberration prediction consists of two steps. The first step is prediction of the diffraction map on the projection pupil. The second step is computing thermal aberration from the diffraction map using a lens thermal model and an aberration correction function. We performed a verification test for ThAO using a mask of 1x-nm memory and strong off-axis illumination. We clarified the current performance of thermal aberration prediction, and also confirmed that the impacts of thermal aberration of NSR-S621D on CD and overlay for our 1x-nm memory pattern are very small. Accurate thermal aberration prediction with ThAO will enable thermal aberration risk-free lithography for semiconductor chip production.

In this work compact optical proximity correction (OPC) model optimization methodology is presented. The methodology requires less measured empirical (wafer) metrology data for model calibration than conventional approaches, but still enables successful compact OPC model building which can be extrapolated to various process conditions within a focus-exposure matrix (FEM). In order to ensure compact modeling success, a rigorous modeling technique is incorporated in the modeling flow for generation of additional emulated data. The emulated data, along with original empirical data, are used in the compact OPC model optimization process. The presented methodology couples rigorous and compact modeling, to reduce both need of large quantities of empirical data collected from test wafers, and metrology noise impact on model calibration processes, and as well as increases accurate and predictable compact models throughput. Initial tests have shown that by using 5x less empirical data, the presented methodology results a compact OPC model which is in excellent agreement with a model that had been calibrated using the full empirical data set.

Scanner matching based on CD or patterning contours has been demonstrated in past works. All of these published works require extensive wafer metrology. In contrast, this work extends a previously proposed optical pattern matching method that requires little metrology by adding the component requirements and the procedure for creating an automation flow. In a test case, we matched an ASML XT:1900i using a DOE to an ASML NXT:1950i scanner using FlexRay. The matching was conducted on a 4x nm process test layer as a development vehicle for the 2x nm product nodes. The paper summarizes the before and after matching data and analysis, with future opportunities for improvements suggested.

In the optical microlithography in concern, a digital micromirror device plays the role of a digital mask, and the diffraction effect due to reflections off of a square micromirror may not be negligible. The projected beam image may not be a typical uniform square or pointed circular beam. Therefore, existing image decomposition modes and reflection criteria developed for a typical beam may not be appropriate for lithography under the diffraction effect. In this study, to improve the critical dimension uniformity and the exposure dose effectiveness, a novel image decomposition mode based on the proxy delta configuration is proposed. A successive set of proxy delta parameters which produce a honeycomb decomposed structure is utilized to implement a proxy delta lithography system that allows the usage of a typical square image array without the hassle of projecting a square mirror array into a rectangular image array using an aspheric micro lens array. A reflection criterion employing intensity weighted occupancy patterns that account for the diffracted beam profile is utilized to adjust the binary reflections. The potential for a honeycomb decomposition mode based on the proposed proxy delta configuration to improve the critical dimension uniformity and the exposure dose effectiveness is demonstrated.

Spacer based SADP (Self-Aligned Double Patterning) is used increasingly in IC manufacturing as design rules outstrip the resolution capabilities of traditional single exposure lithography processes. In this paper, a 15nm half pitch SADP process based upon an EUV single exposure produced mandrel is modeled using commercial simulation software (PROLITH X4.2, KLA-Tencor corp.). Good accuracy is observed when the simulated results are compared to actual experimental results. Artifacts present in the final spacer pattern are clearly traceable to the resist imaging step.

Self-aligned multiple patterning (SAMP) techniques can potentially scale integrated circuits down to half-pitch 7nm. In this paper, we present a comparative analysis of self-aligned quadruple (SAQP) and sextuple (SASP) techniques by investigating their technological merits and limitations, process complexity and cost structures, strategy of layout decomposition/synthesis, and yield impacts. It is shown that SASP process complexity is comparable to that of SAQP process, while it offers 50% gain in feature density and may be extended for one more node. The overlay yield of cut process is identified to be a challenge when the minimum device feature is scaled to half-pitch 7nm. The mask design issues for various applications using each technique are discussed, and the corresponding layout decomposition/synthesis strategy for complex 2D patterning is proposed. Although the high-dose EUV single-cut process can save significant costs when applied to replace the 193i multiple-cut process to form fin/gate structures, our cost modeling results show that SADP+EUV approach is still not cost effective for patterning other critical layers that generally require the same mask number (and lithographic steps) as the non-EUV schemes.

Grayscale lithography has become a common technique for three dimensional structuring of substrates. In order to make the process useful for manufacturing of semiconductor and in particular optoelectronic devices, high reproducible and uniform final film thicknesses are required. Simulations based on a calibrated resist model are used to predict customized process parameters from pixel layout to 3d substrate patterning. Multiple, arbitrary resist heights are reached by using i-line lithography. Scalable and uniform transfer of discrete step heights into oxide are realized by multiple alternating high selective resist and oxide (MASO) etch. Requirements and limitations of reliable 3D film thickness and uniformity control within a CMOS fabrication environment are being discussed.

Publisher’s Note: This paper, originally published on 4/12/2013, was replaced with a corrected/revised version on 9/29/2015. If you downloaded the original PDF but are unable to access the revision, please contact SPIE Digital Library Customer Service for assistance.

As 193 nm immersion lithography may be required to be extended beyond 20 nm node, multiple patterning lithography will become a necessity in that scenario. We present a cost-effective approach for 22 nm half-pitch double patterning, with extendibility to sub-10 nm half-pitch pitch division. Spacers on sufficiently sloped sidewalls directly transferred from a low-contrast photoresist profile can be removed by anisotropic etching. Alternatively, spacer gaps for defining trenches may be prevented from penetrating to the substrate by the use of sloped sidewalls. These sloped sidewalls are defined by attenuated phase shift mask (attPSM) features which impart phase shifts other than 180 or 0 degrees. Such features can be accommodated in the process flow for fabricating phase shift masks by the definition of one or two extra layers of processing in the mask shop. Aerial image simulations show this photomask design is more effective in generating sloped foot profiles in the photoresist than simply using sub-resolution features or reducing the width of the clear region. Loop trimming and sidewall spacer definition are accomplished in a single photomask. In addition, there is now an extra ability to define random, arbitrary breaks in the spacer-defined pattern, without using an extra exposure for specified cuts. In this way, a single exposure of a low-contrast photoresist around the sensitivity limit using a modified attenuated phase-shift photomask is sufficient to pattern regularly arranged spacer-defined lines at fixed pitch with irregularly arranged breaks, or 'cuts' in the lines.

For patterning the upper Metal layers of the 10 nm node, Spacer Is Dielectric (SID) Patterning is the leading candidate. Compared to Litho-Etch-Litho-Etch Double Patterning, SID has lower line-width roughness, tighter line-end spacing, and lower sensitivity to overlay errors. However, SID places more restrictions on design, and creates wafer-printing artifacts or “spurs.” These printing artifacts arise because SID uses a subtractive trim etch to create “negative contours,” which are very different from the positive contours of single-exposure patterning. In this work, we show the origin of these spurs, and present rule-based decomposition methods to avoid or mitigate them.

The low-k1 domain of immersion lithography tends to result in much smaller depths of focus (DoF) compared to prior technology nodes. For 28 nm technology and beyond it is a challenge since (metal) layers have to deal with a wide range of structures. Beside the high variety of features, the reticle induced (mask 3D) effects became non-negligible. These mask 3D effects lead to best focus shift. In order to enhance the overlapping DoF, so called usable DoF (uDoF), alignment of each individual features best focus is required. So means the mitigation of the best focus shift. This study investigates the impact of mask 3D effects and the ability to correct the wavefront in order to extend the uDoF. The generation of the wavefront correction map is possible by using computational lithographic such Tachyon simulations software (from Brion). And inside the scanner the wavefront optimization is feasible by applying a projection lens modulator, FlexWave^TM (by ASML). This study explores both the computational lithography and scanner wavefront correction capabilities. In the first part of this work, simulations are conducted based on the determination and mitigation of best focus shift (coming from mask 3D effects) so as to improve the uDoF. In order to validate the feasibility of best focus shift decrease by wavefront tuning and mitigation results, the wavefront optimization provided correction maps are introduced into a rigorous simulator. Finally these results on best focus shift and uDoF are compared to wafers exposed using FlexWave then measured by scanning electron microscopy (SEM).

From 28nm technology node and below, Optical Proximity Correction (OPC) needs to take into account light scattering effects from prior layers when bottom anti-reflective coating (BARC) is not used, which is typical for implant layers. In this paper, we implement a sub-layer aware simulation method into a verification tool for Optical Rule Check (ORC) that is used on full 28nm test chip. The sub-layer aware verification can predict defects that are missed by standard ORC. SEM-CD review and defectivity analysis were used to confirm the validity of the sub-layer aware model on wafer.

This paper discusses the CD Bossung tilt phenomena in low-k1 lithography using interference harmonics and rigorous EM spectrum analysis. Interference harmonics analysis is introduced to explain the interaction of diffraction orders in the focal region leading to this abnormal CD behavior. This method decomposes the vector image formula into a superposition of cosine components to describe the interference of diffraction orders. The symmetry properties of components of an optical projection system were investigated to find out three potential sources for the asymmetric Bossung behavior, namely mask 3D (M3D) effect, lens aberration, and wafer reflectivity. Under good lens aberration and substrate reflectivity controls, the M3D effect accounts for most of the CD Bossung tilt. A rigorous EM mask spectral analysis was performed to reveal the impact of mask topography on the near-field intensity of mask transmission and the far-field image formation. From the analysis, the asymmetric phase distribution in the mask spectrum is the root cause for CD Bossung tilt. Using both the interference harmonics and the rigorous EM spectrum analysis, the effect of various resolution enhancement techniques (RET) to the Bossung tilt is also studied to find the best RET combination for M3D immunity. In addition, a pupil optimization algorithm based on these two analyses is proposed to generate the phase compensation map for M3D effect counteraction.

As EUV Lithography is not ready yet for sub-20nm node manufacturing, ArF immersion lithography must extend its capability. Among various double patterning techniques already explored, Litho-Etch-Litho-Etch (LELE) is one of the main streams considered today to continue scaling at 20nm and below. Our paper presents an application of a new OPC algorithm designed to ensure a successful double patterning process at 20nm node. A novel OPC technique was applied to 20nm contact and M1 layers. It is intended for both double and multi-patterning lithography technologies providing model based capability for concurrent correction of the split layouts ensuring a robust stitching overlap of the cut features and preventing inter-mask bridging. We have also developed an OPC verification methodology for DP failures due to dose, focus, mask and overlay errors. One of the most critical challenges of DP technology is: ensuring sufficient stitching of the cut design shapes and preventing a risk of inter-mask shape bridging. This problem is rapidly exacerbated by the overlay error. It is demonstrated that the new OPC algorithm results in enhanced stitching overlap and a good space control between inter-mask shapes, thus, minimizing DP process implications on circuit reliability.

Compact mask models provide an alternative to speed up rigorous mask diffraction computation based on electromagnetic field (EMF) modeling. The high time expense of the rigorous mask models in the simulation process challenges the exploration of innovative modeling techniques to compromise accuracy and speed in the computation of the diffracted field and vectorial imaging in optical lithographic systems. The Artificial Neural Network (ANN) approach is presented as an alternative to retrieve the spectrum of the mask layout in an accurate yet efficient way. The validity of the ANN for different illuminations, feature sizes, pitches and shapes is investigated. The evaluation of the performance of this approach is performed by a process windows analysis, comparison of the spectra, best focus and critical dimension (CD) through pitch. The application of various layouts demonstrated that the ANN can also be trained with different patterns to reproduce various effects such as: shift of the line position, different linewidths and line ends. Comparisons of the ANN approach with other compact models such as boundary layer model, pulses modification, spectrum correction and pupil filtering techniques are presented.

While critical lithographic feature size diminishes, resist profile can vary significantly as image varies. As a consequence, the final etch results are becoming more dependent on 3D resist profile rather than only a simple 2D resist image as an etch mask. Therefore, it has become necessary to build resist profile information into OPC models, which traditionally only contain 2D information in the x-y plane. At the same time, rigorous lithographic simulators are capable of modeling 3D resist profiles on a small chip area. In this work, one approach is investigated to account for 3D resist profile characteristics in full-chip OPC models with the assistance of rigorous simulation. With measurement data collected from experimental wafers, a rigorous resist model is first calibrated and verified. Then individual compact models are built to match the rigorous resist model profile at specified resist heights. The calibrated compact model for bottom resist line width corresponds to a conventional OPC model while resist profile is described by multiple models specified for certain resist heights, with each model being in the form of conventional compact models. In practice, the bottom model along with one or two models at critical heights are usually sufficient to detect sites where etch results become sensitive to resist profile. It has been found that the rigorous resist profile model can be well matched by the suggested compact models. For a quick application demonstration, hot spots of the etch results in the test case have been shown to be successfully captured by the calibrated compact models.

We evaluate the accuracy of the simulated aerial image computed using different types of Fourier transform: the Continuous Fourier transform (CFT), continuous Fourier series (CFS) and discrete Fourier transform (DFT), the transform currently used in practise. Lithography simulation necessitates efficient algorithms to accurately estimate the Fourier transform. The rectilinear mask structure can be used to compute the CFS efficiently, in most cases much faster than the DFT. We present a rigorous analysis and comparison of FFT-simulated aerial image and CFS-simulated aerial image. We also present the conditions under which the most accurate simulated aerial image for each type of Fourier transform can be obtained. We show that there are two main sources of inaccuracy in the computation of aerial image using the DFT. First, we establish that aliasing from the inherent discontinuity of rectilinear polygons is the main source of inaccuracy. We show the conditions under which this results in an over-estimate or underestimate of the Critical Dimension (CD). We thus describe how to perform aliasing-minimizing sampling. This adapts the sampling to the polygon pattern of the mask, by ensuring each discontinuity is exactly at the middle of two consecutive samples. Second, we show that sampling at twice the Nyquist rate of the filtered signal can in practise circumvent the inaccuracy due to the approximation of the integral by a discrete sum.

With ever shrinking critical dimensions, half nm OPC errors are a primary focus for process improvement in computational lithography. Among many error sources for 2x and 1x nodes, 3D mask modeling has caught the attention of engineers and scientists as a method to reduce errors at these nodes. While the benefits of 3D mask modeling are well known, there will be a runtime penalty of 30-40% that needs to be weighed against the benefit of optical model accuracy improvements. The economically beneficial node to adopt 3D mask modeling has to be determined by balancing these factors. In this paper, a benchmarking study has been conducted on a 20nm cut mask, metal and via layers with two different computational lithography approaches as compared with standard thin-mask approximation modeling. Besides basic RMS error metrics for model calibration and verification, through pitch and through size optical proximity behavior, through focus model predictability, best focus prediction and common DOF prediction are thoroughly evaluated. Runtime impact and OPC accuracy are also studied.

Computational lithography has become indispensable when developing lithography solutions for advanced technology nodes. One of the essential instruments for optimizing full-chip process windows (PW) is source mask optimization (SMO). To avoid model calibration for each new optimized source, separable resist models need to be created such that a reliable model can be obtained simply by replacing the source in the existing OPC model. In this paper we start from a fully calibrated resist model and optimize a new source for which we want to create a reliable OPC model. Relying on the separability of the model, the initial illumination source is replaced by the new one while not changing any resist model parameters. In order to reach the accuracy needed for OPC, the best focus and best dose still need to be accurately determined. We will investigate two models that have the same new SMO source and original resist model. For one model the best focus and dose are determined by the simulated Bossung plot of one anchor feature. The second model’s best focus and exposure are determined by a small set of FEM experimental data. The quality of these two models is then evaluated by comparing them to a reference model, which is fully calibrated using a complete dataset for the new source. We show that the calibrated FEM OPC model can be extrapolated by simply changing the source. A limited amount of experimental FEM data is required to accurately determine the best focus and exposure for the new source. Best focus and exposure based on the anchor pattern simulation has a higher degree of uncertainty compared to a small set of experimental data.

Of keen interest to the IC industry are advanced computational lithography applications such as Optical Proximity Correction, OPC, Optical Proximity Effect matching, OPEM, and Source-Mask Optimization, SMO. Lithographic mask models used by these simulators and their interactions with scanner illuminator models are key drivers impacting the accuracy of the image predications of the computational lithography applications. To construct topographic mask model for hyper-NA scanner, the interactions of the fields with the mask topography have to be accounted for by numerically solving Maxwell’s equations. The simulators used to predict the image formation in the hyper-NA scanners have to rigorously treat the topographic masks and the interaction of the mask topography with the scanner illuminators. Such mask models come at a high computational cost and pose challenging accuracy vs. compute time tradeoffs. To address the high costs of the computational lithography for hyper-NA scanners, we have adopted Reduced Basis, RB, method to efficiently extract accurate, near field images from a modest sample of rigorous, Finite Element, FE, solutions of Maxwell’s equations for the topographic masks. The combination of RB and FE methods provides means to efficiently generate near filed images of the topographic masks illuminated at oblique angles representing complex illuminator designs. The RB method’s ability to provide reliable results from a small set of pre-computed, rigorous results provides potentially tremendous computational cost advantage. In this report we present RB/FE technique and discuss the accuracy vs. compute time tradeoffs of hyper-NA imaging models incorporating topographic mask images obtained with the RB/FE method. The examples we present are representative of the analysis of the optical proximity effects for the current generation of IC designs.

The Domain Decomposition Method (DDM) for approximating the impact of 3DEMF effects was introduced nearly ten years ago as an approach to deliver good accuracy for rapid simulation of full-chip applications. This approximation, which treats mask edges as independent from one another, provided improved model accuracy over the traditional Kirchhoff thin mask model for the case of alternating aperture phase shift masks which featured severe mask topography. This aggressive PSM technology was not widely deployed in manufacturing, and with the advent of thinner absorbing layers, the impact of mask topography has been relatively well contained through the 32 nm technology node, where Kirchhoff mask models have proved effective. At 20 nm and below, however, the thin mask approximation leads to larger errors, and the DDM model is seen to be effective in providing a more accurate representation of the aerial image. The original DDM model assumes normal incidence, and a subsequent version incorporates signals from oblique angles. As mask dimensions become smaller, the assumption of non-interacting mask edges breaks down, and a further refinement of the model is required to account for edge to edge cross talk. In this study, we evaluate the progression of improvements in modeling mask 3DEMF effects by comparing to rigorous simulation results. It is shown that edge to edge interactions can be accurately accounted for in the modified DDM library. A methodology is presented for the generation of an accurate 3DEMF model library which can be used in full chip OPC correction.

3D Resist Models are gaining significant interest for advanced technology node development. Correct prediction of resist profiles, resist top-loss and top-rounding are acquiring higher importance in ORC hotspot verification due to impact on etch resistance and post etch results. We would like to highlight the specific calibration procedure to calibrate a rigorous 3D model. Special focus is on the importance of high quality metrology data for both a successful calibration and for allowing a reduction of the number of data points used for calibration [1]. In a productive application the calibration could be performed using a subset of 20 features measured through dose and focus and model validation was done with 500 features through dose and focus. This data reduction minimized the actual calibration effort of the 3D resist model and enabled calibration run times of less than one hour. The successful validation with the complete data set showed that the data reduction did not cause over- fitting of the model. The model is applied and verified at hotspots showing defects such as bottom bridging or top loss that would not be visible in a 2D resist model. The model performance is also evaluated with a conventional CD error metric where CD at Bottom of simulation and measurement are compared. We could achieve excellent results for both metrics using SEM CD, SEM images, AFM measurements and wafer cross sections. Additional modeling criterion is resist model portability. A prerequisite is the separability of resist model and optical model, i.e. the resist model shall characterize the resist only and should not lump characteristics from the optical model. This is a requirement to port the resist model to different optical setups such as another illumination source without the need of re-calibration. Resist model portability is shown by validation and application of the model to a second process with significantly different optical settings. The resist model can predict hot spots and CDs for the second litho process with the same quality as for the process it was calibrated to.

In recent years, demand for high-density integration of semiconductor chips has steadily increased due to miniaturization and high-performance requirements of electronics including Smartphones and Tablet PCs. In addition to 3D integration using Through-Silicon Via (TSV) technology, 2.5D integration technology using silicon interposers has also become a hot topic. Canon has identified key challenges that must be solved for successful implementation of high-density integration technologies into mass production and to meet these challenges, Canon developed the FPA-5510iV i-line lithography tool (stepper) that is now in wide use at customer sites for their most challenging processes. In this paper, Canon will explain details of FPA-5510iV features that support high-density integration. Canon will also introduce additional challenges that must be solved to ensure the success of high-density integration technologies in mass production, as well as Canon efforts to solve the remaining challenges.

193nm ArF excimer lasers are widely used as light sources for the lithography process of semiconductor production. At first, ArF excimer lasers have been used in semiconductor productions at the 90nm node and recently ArF excimer lasers have begun to be used for the 32nm node, by the progress in the immersion technology and the double-patterning technology. Furthermore, considering current status of development of the lithography technology using a next-generation light source, or extreme ultraviolet (EUV) light source, the start of mass production with the next-generation light source is estimated to start from 2015. Therefore, there is a need for extension of 193nm immersion lithography technology. By using the multi-patterning and double-patterning technology, design rules below limit at single exposure is possible. However, throughput is reduced due to increased lithography processes. In order to improve a decrease in throughput, a high power ArF excimer laser and larger size wafer (450mm in diameter) is needed. We have developed a new high power laser with the concept of eco-friendly. In this paper, we will introduce technologies used for our latest ArF excimer laser having tunable output power between 90W and 120W and report its performance data.

Demand for increased semiconductor device performance at low cost continues to drive the requirements for shrinking the geometry of features printed on silicon wafers. Argon fluoride (ArF) excimer laser systems operating at 193 nm and producing high output power played a key role in patterning of the most advanced features for high volume deep ultraviolet (DUV) lithography over the last decade. Lithographic patterning has progressed from ArF dry to ArF immersion (ArFi) to double and multiple patterning applications, with increasingly tight requirements for the quality of light at 193 nm and improved system reliability. This drove the transition from single chamber laser systems to dual chamber systems with ring cavity amplifier architectures. We are presenting a flexible 90-120W ArFi excimer laser system, developed for high volume multiple patterning manufacturing as well as 450mm wafer applications. Light source design is based on dual-chamber architecture with ring cavity power amplifier.

Accurate overlay with high throughput is the key to success in multiple-patterning lithography. To achieve accurate overlay, the imaging system must control and minimize the thermal aberration and distortion. There are several sources of thermal aberration in an immersion lithography system: (1) reticle deformation by reticle heating; (2) air temperature fluctuation near the reticle; (3) thermal aberrations from the projection lens; and (4) immersion water temperature fluctuation. All aberrations and distortion are impacted by these sources and need to be minimized for accurate overlay. In this paper, we introduce our approach and technologies for the control of thermal aberrations.

Immersion lithography is being extended to the 20-nm and 14-nm node and the lithography performance requirements need to be tightened further to enable this shrink. In this paper we present an integral method to enable high-order fieldto- field corrections for both imaging and overlay, and we show that this method improves the performance with 20% - 50%. The lithography architecture we build for these higher order corrections connects the dynamic scanner actuators with the angle resolved scatterometer via a separate application server. Improvements of CD uniformity are based on enabling the use of freeform intra-field dose actuator and field-to-field control of focus. The feedback control loop uses CD and focus targets placed on the production mask. For the overlay metrology we use small in-die diffraction based overlay targets. Improvements of overlay are based on using the high order intra-field correction actuators on a field-tofield basis. We use this to reduce the machine matching error, extending the heating control and extending the correction capability for process induced errors.

NSR-S622D, Nikon’s new ArF immersion scanner, provides the best and practicable solutions to meet the escalating requirement from device manufactures to accommodate the further miniaturization of device pattern. NSR-S622D has various additional functions compared to the previous model such as the newly developed illumination system, new projection lens, new AF system new wafer table in addition to the matured Streamlign platform. These new features will derive the outstanding performance of NSR, enabling highly controlled CD uniformity, focus accuracy and overlay accuracy. NSR-S622D will provide the adequate capabilities that are demanded from a lithography tool for production of 1x nm hp node and beyond.

In this paper we report on the performance enhancements on the NXT immersion scanner platform to support the immersion lithography roadmap. We particular discuss scanner modules that enable future overlay and focus requirements. Among others we describe the improvements in grid calibrations and grid matching; thermal control of reticle heating with dynamic systems adjustments; aberration tuning and FlexWave-lens heating control as well as aberration- and overlay-metrology on wafer-2-wafer timescales. Finally we address reduction of leveling process dependencies, stage servo dynamics and wafer table flatness to enhance on-product focus and leveling performance. We present and discuss module- and system-data of the above mentioned scanner improvements.

It is evident that as industry moves towards 28 and 20 nm large scale production, more flexibility in source is eminent for better process margin. In this paper, we review different realms of illumination optimization techniques with combinations of currently available source shapes along with pixelated source optimization. However, it has been observed in the past that any optimized source heavily relies on the patterns that are used in optimization. Therefore, it is critical that early in the resolution enhancement technology (RET) selection flow, test patterns are carefully chosen. The patterns should maintain the balance of cycle time for source tuning and at the same time ensure fidelity in accuracy. This type of trade-off becomes easier with an automated pattern selection tool that can guarantee coverage and accuracy together. Different approaches of pattern selection are demonstrated in this paper and the knowledge is transferred to development activities for 28 nm layers. In this paper we investigate compatibility of sources that are tuned over a set of design database and its adaptability of optimized source over small variations in design. At the end we demonstrate a reliable solution that could be integrated early in RET development and easily adapted for the production environment.

For 28 nm technology node and below resist profiles need to be taken in to consideration during optical proximity correction (OPC) and verification. The low k1 results in a shallower depth of focus and thus thinner resists, which combined with the process limits increases the risk of resist degradation. Only considering the resist critical dimensions at a single focal plane (such as at the bottom of the resist stack) will miss the impact of the resist 3D profile, like top loss or bottom footing, which can transfer to etch hard pattern failures. To date, modeling to study resist 3D profiles has been available using rigorous simulators and has been used as a verification method for hot spots captured during full chip OPC verification, but not for full chip verification due to the high computational run time cost. This paper demonstrates a 3D resist compact OPC model concept and implementation in a full chip OPC and verification flow. The results show significant improvement for full chip OPC quality with a good correlation between simulation and real wafer hot spots. Because resist profiles are not directly correlated to etch failure, the relationship between the resist profile and etch failures and how to characterize the threshold to dispose the hot spots for the 3D compact model was also investigated.

In this paper we describe an approach for the realization of 3D resist patterns for implant applications, highlighting the opportunities of controlling doping depth and profiles and their influence on device parameters. We choose a grayscale litho process, where the 3D structuring of the photoresist is done by a spatially variable exposure. Pixilated grayscale mask structures are defined to achieve the desired 3D resist patterns by locally variable transmittance values. The variable transmittance values result in different resist film thicknesses after development. Up to 20 different resist film thicknesses are obtained within a single exposure shot. This enables spatial patterning of the implant depth and accordingly various novel approaches for device optimization.

We report that, based on our experimental data, lens heating (LH) impact on wafer image can be effectively controlled by using a computational method (cASCAL) on critical device layers with no request on tool time. As design rule shrinks down, LH control plays a key role in preventing the image deterioration caused by the LH-induced wavefront distortion during exposure. To improve LH prediction accuracy, 3-dimension structure of mask stack (M3D) is considered in calculating the electro-magnetic (EM) field that passes through the mask for full chip. Additionally, lens specific calibration (LSC) is performed on individual scanners to take the lens-to-lens variation into account. In data comparisons, we show that cASCAL performs very well as an ASCAL substitute, and that M3D and LSC improve the LH prediction accuracy of cASCAL.

Assuming that all exposure tools on which a certain production reticle is being used are from same type and configuration it can be expected that the performance of the reticle should be independent from the exposing machines. When planning or performing arrangements for process transfer between different production sites or capacity expansion within one site performing a proximity matching between different exposure tools is a common activity. One of the objectives of a robust optical proximity correction (OPC) model is to simulate the process variation. Normally, the wafer critical dimension (CD) calibration of an OPC model is applied for one specific scanner first. In order to enhance the tolerance of the OPC model so called fingerprints of different scanners should be matched as closely as possible. Some examples of features for fingerprint test patterns are “critical dimension through pitch” (CDTP), “inverse CDTP”, “tipto-tip” and “linearity patterns”, and CD difference of disposition structures. All of them should also be matched as tightly as possible in order to reduce the process variation and to strengthen the tolerance of an OPC model. However, the focus difference between nested and isolated features which is directly influenced by different exposure tools and reticle layers will have an effect on the proximity matching of some patterns such as inverse CDTP and uniformly distributed disposition structures. In this manuscript the effects of focus differences between nested and isolated features for scanner proximity matching will be demonstrated. Moreover, the results for several scanners and different mask layers using advanced binary mask blank material will also be investigated. Even if some parts of the proximity features are closely enough to each other different parity proximity patterns will be affected by the focus difference between dense and isolated features. Because the focus difference between isolated and dense features is dependent on the illumination conditions, different mask layers applied for a proximity correction will lead to different results. The effects of source variations causing isolated and dense feature focus differences between scanners for 28 nm poly, 1X metal and contact layers will be illustrated.

Source mask optimization (SMO) is considered to be one of the technologies to push conventional 193nm lithography to its ultimate limits. In comparison with other SMO methods that use an inverse problem formulation, SMO based on genetic algorithm (GA) requires very little knowledge of the process, and has the advantage of flexible problem formulation. Recent publications on SMO using a GA employ a binary-coded GA. In general, the performance of a GA depends not only on the merit or fitness function, but also on the parameters, operators and their algorithmic implementation. In this paper, we propose a SMO method using real-coded GA where the source and mask solutions are represented by floating point strings instead of bit strings. Besides from that, the selection, crossover, and mutation operators are replaced by corresponding floating-point versions. Both binary-coded and real-coded genetic algorithms were implemented in two versions of SMO and compared in numerical experiments, where the target patterns are staggered contact holes and a logic pattern with critical dimensions of 100 nm, respectively. The results demonstrate the performance improvement of the real-coded GA in comparison to the binary-coded version. Specifically, these improvements can be seen in a better convergence behavior. For example, the numerical experiments for the logic pattern showed that the average number of generations to converge to a proper fitness of 6.0 using the real-coded method is 61.8% (100 generations) less than that using binary-coded method.

It is a distinctive feature of the metal contact layout in NAND flash memory devices that there are small-pitch contact patterns and random-pitch contact patterns in one layout. This kind of pitch difference between cell array patterns and isolated single patterns hadn’t had a decisive effect on wafers when the illumination condition is not aggressive. However, the pattern pitch difference has caused various problems including the best focus shift due to extreme illuminations. The common DOF margin of a contact layout is degraded when the best focus depth for each pattern is variable. Mask topography effect is well known for the major cause of best focus shift between contact patterns which have different pitches. The demand for device technology node shrink for production cost reduction has required adoption of hyper NA illumination conditions, and this aggressive illumination made it hard to secure an enough common DOF margin due to the best focus shift. In this work, the best focus shift phenomenon among different-pitch patterns caused by mask 3D effects is studied according to the various illumination conditions. It is found that the more aggressive illumination condition is and the bigger the pitch difference among patterns in one layout is, the bigger the best focus shift become. Also, we suggest the solution for avoiding this DOF margin degradation, which is SRAF optimization.

Post exposure bake (PEB) Diffusion effect is one of the most difficult issues in modeling chemically amplified resists. These model equations result in a system of nonlinear partial differential equations describing the time rate of change reaction and diffusion. Verifying such models are difficult, so numerical simulations are needed to solve the model equations. In this paper, we propose a high speed 3D resist image simulation algorithm based on a novel method to solve the PEB Diffusion equation. Our major discovery is that the matrix formulation of the diffusion equation under the Crank– Nicolson scheme can be derived into a special form, AX+XB=C, where the X matrix is a 3D resist image after diffusion effect, A and B matrices contain the diffusion coefficients and the space relationship between directions x, y and z. These matrices are sparse, symmetric and diagonal dominant. The C matrix is the last time-step resist image. The Sylvester equation can be reduced to another form as (I⊗A + B^T⊗I) X =C, in which the operator ⊗ is the Kronecker product notation. Compared with a traditional convolution method, our method is more useful in a way that boundary conditions can be more flexible. From our experimental results, we see that the error of the convolution method can be as high as 30% at borders of the design pattern. Furthermore, since the PEB temperature may not be uniform at multi-zone PEB, the convolution method might not be directly applicable in this scenario. Our method is about 20 times faster than the convolution method for a single time step (2 seconds) as illustrated in the attached figure. To simulate 50 seconds of the flexible PEB diffusion process, our method only takes 210 seconds with a convolution set up for a 1240×1240 working area. We use the typical 45nm immersion lithography in our work. The exposure wavelength is set to 193nm; the NA is 1.3775; and the diffusion coefficient is 1.455×10^-17m²/s at PEB temperature 150°C along with PEB time 50 seconds with image resolution setup to be 1240×1240.

Line edge roughness (LER) is a common problem to most lithography approaches and is seen as the main resolution limiter for advanced technology nodes¹. There are several contributors to LER such as chemical/optical shot noise, random nature of acid diffusion, development process, and concentration of acid generator/base quencher. Since interference-like lithography (IL) is used to define one directional gridded patterns, some LER mitigation approaches specific to IL-like imaging can be explored. Two methods investigated in this work for this goal are (i) translational image averaging along the line direction and (ii) pupil plane filtering. Experiments regarding the former were performed on both interferometric and projection lithography systems. Projection lithography experiments showed a small amount of reduction in low/mid frequency LER value for image averaged cases at pitch of 150 nm (193 nm illumination, 0.93 NA) with less change for smaller pitches. Aerial image smearing did not significantly increase LER since it was directional. Simulation showed less than 1% reduction in NILS (compared to a static, smooth mask equivalent) with ideal alignment. In addition, description of pupil plane filtering on the transfer of mask roughness is given. When astigmatism-like aberrations were introduced in the pupil, transfer of mask roughness is decreased at best focus. It is important to exclude main diffraction orders from the filtering to prevent contrast and NILS loss. These ideas can be valuable as projection lithography approaches to conditions similar to IL (e.g. strong RET methods).

The k1 factor continues to be driven downwards; the Extreme Ultra Violet Lithography (EUVL) should be a powerful solution for 2xnm node. But, EUVL is not ready for 2xnm node manufacturing currently. Therefore, we must extend ArF immersion capability on 2xnm devices. In order to enable the features/patterns of 20nm node and beyond, Mask Error Enhancement Factor (MEEF) and Depth of Focus (DoF) play an important role for continuing shrinking designs in the low-k1 lithography. Lithography optimization by RET (Resolution Enhancement Techniques) application is essential to obtain a usable process window (PW). SMO (Source Mask Optimization) [1] is a RET solution for better total process window improvement on 20nm node and beyond. Using these concern patterns of design rule, the optimal source with optical balance would be generated. The wafer result by using the optimal source need to be checked and compare with simulation result. In this paper, we will introduce how to use SMO in Cont lithography process development on 20nm node. The SMO of pattern split with PTD (Positive Tone Develop), single exposure with PTD (Positive Tone Develop) and single exposure of NTD (Negative Tone Develop) had been studied. Pattern split with PTD can provide an enough process window. But, it suffers overlay control and process cost issue. Single exposure is a good solution to fix overlay control and process cost. But it suffers low process window. Hence, single exposure with PTD is another choice to improve the process window. Base on our study, NTD SMO has better performance (DoF: ~20 increase, MEEF: ~10 decrease) than PTD SMO on single exposure process. The detail result will be shown in this paper.

Contact-hole patterning is even more challenging than line/space patterning because of the lower image contrast and smaller process window. To enable single exposure solution of 40-45nm half pitch contact-hole at this nearly resolvable limit of current 1.35NA ArF immersion lithography, negative tone development (NTD) process, source mask co-optimization (SMO) methodology and free-form source were explored in this study. The optimization of free form source and mask for NTD process was firstly carried out via Brion Tachyon SMO^TM software. The wafer-level performance was then compared for different mask layout solutions and different mask types. A manufacture worthy process window was achieved for 40nm technology node Flash memory product through the combination of free-from source, SMO and NTD technologies. In the performance comparison for mask types, 6% HTPSM performed wider DoF and exposure latitude for all three pitch designs. But OMOG mask is superior to 6% HTPSM on mask and wafer CD uniformity. To further improve the overlapping process window, preserving the SMO layout solution as possible for the sparse environments and minimizing the SRAF writing errors were proposed as the two most critical tuning knobs.

To avoid the dramatically diminishing of lithography process window as the shrink of design rule, the implementation of process-aware optical proximity correction (PWOPC) has been indispensable. The conventional PWOPC is capable of reducing CD variation at off-focus-off-dose conditions for the worst hotspot but some new weak points might be generated due to over compensation from compromising with the worst hotspot. In this paper, a so-called “multiple-step process aware OPC”, was demonstrated for maintaining better process window for all hotspots via damascene metal layer in 43nm half-pitch design. Through isolating the hotspots from the chip layout, different CD tolerances can be applied for the various types of hotspots to avoid the conflicts between different requirements. Increased levels of CD-tolerance could be applied in the multiple-step PWOPC flow for the layout with a great number of weak points. The ultimate aim of the multiple-step PWOPC operation is maintaining sufficient process window for entire layout. The performance comparison was carried out among nominal OPC, conventional PWOPC and multiple-step PWOPC flows for contour CD within appropriate process window, turn around time of layout correction and CD distribution of hotspots.

In advanced 20nm and below technology nodes, the mask enhanced error factor (MEEF) plays an important rule due to the request of stable process control and quality of mask manufacture. It provides us an effective parameter to analyze the process window for lithography. In advanced nodes, MEEF criterion becomes more important than previous nodes because very tight process tolerance is requested, especially in OPC and mask capability control. Therefore, we have to do further studies on this topic. In the simple line/trench design layers (for example: Active and poly), the MEEF is easy to be defined because mask bias is isotropic. However, in the complicated two-dimensional (2D) design layers (for example: Contact and Mvia), they are hard to be defined a suitable definition of MEEF. In the first part, we used the global bias to calculate the MEEF on all patterns. It makes calculation easier to compare with other patterns which are different shapes. However, when we inspected the 2D line-end patterns on the wafer, we found the significant differences between the MEEF of wafer data and aerial simulation. In order to clarify this issue, we perform series simulation studies of the line-end MEEF. Then we knew that it came from the different bias strategies. Furthermore, the simulation studies show that the line-end MEEF of non-preferable orientation is very sensitive to mask X/Y ratio bias due to strong OAI optical behavior by the SMO source. As a result, a new point of view of 2D MEEF is suggested according to physical mask CD error measurement data. In this study, we would find a better description of the MEEF than traditional one for lithographic process development on 2D region.

In this paper, we propose a new regularization framework that regularizes mask directly by applying a mask filtering technique to improve computational efficiency and enhance mask manufacturability for pixel-based Inverse Lithography Technique (ILT). Generally, the synthesized mask by pixel-based ILT is a grey-level image, and possesses small, unwanted block objects, such as isolated holes, protrusions, and jagged edges, which are unreachable in the real manufacturing process. The proposed method filters (or regularizes) mask directly to guarantee manufacturability of the synthesized mask pattern; this technique is different from the conventional regularization method that regularizes mask by incorporating various penalty functions to a cost function. A tailored mask filter is developed in this special ILT case. In addition, we introduce a new metric, edge distance error which has the same dimension nanometer as edge placement error and has a continuous expression as pattern error, to guide mask synthesis. Simulation results demonstrating the validity and efficiency of the proposed method are presented.

Basic image intensity parameters, like maximum and minimum intensity values (Imin and Imax), image logarithm slope (ILS), normalized image logarithm slope (NILS) and mask error enhancement factor (MEEF) , are well known as indexes of photolithography imaging quality. For full chip verification, hotspot detection is typically based on threshold values for line pinching or bridging. For image intensity parameters it is generally harder to quantify an absolute value to define where the process limit will occur, and at which process stage; lithography, etch or post- CMP. However it is easy to conclude that hot spots captured by image intensity parameters are more susceptible to process variation and very likely to impact yield. In addition these image intensity hot spots can be missed by using resist model verification because the resist model normally is calibrated by the wafer data on a single resist plane and is an empirical model which is trying to fit the resist critical dimension by some mathematic algorithm with combining optical calculation. Also at resolution enhancement technology (RET) development stage, full chip imaging quality check is also a method to qualify RET solution, like Optical Proximity Correct (OPC) performance. To add full chip verification using image intensity parameters is also not as costly as adding one more resist model simulation. From a foundry yield improvement and cost saving perspective, it is valuable to quantify the imaging quality to find design hot spots to correctly define the inline process control margin. This paper studies the correlation between image intensity parameters and process weakness or catastrophic hard failures at different process stages. It also demonstrated how OPC solution can improve full chip image intensity parameters. Rigorous 3D resist profile simulation across the full height of the resist stack was also performed to identify a correlation to the image intensity parameter. A methodology of post-OPC full chip verification is proposed for improving OPC quality at RET development stage and for inline process control and yield improvement at production stage.

To transfer an electronic circuit from design to silicon, a lot of stages are involved in between. As technology evolves, the design shapes are getting closer to each other. Since the wavelength of the lithography process didn't get any better than 193nm, optical interference is a problem that needs to be accounted for by using Optical Proximity Correction (OPC) algorithms. In earlier technologies, simple OPC was applied to the design based on spatial rules. This is not the situation in the recent technologies anymore, since more optical interference took place with the intensive scaling down of the designs. Model-based OPC is a better solution now to produce accurate results, but this comes at the cost of the increased run time. Electronic Design Automation (EDA) companies compete to offer tools that provide both accuracy and run time efficiency. In this paper, we show that optimum usage of some of these tools can ensure OPC accuracy with better run time. The hybrid technique of OPC uses the classic rule-based OPC in a modern fashion to consider the optical parameters, instead of the spatial metrics only. Combined with conventional model-based OPC, the whole flow shows better results in terms of accuracy and run time.

The 193nm immersion lithographic machine has already achieved 22nm node and beyond, and its illuminator has become a polarized and off-axis illumination system. Illumination modes and polarization modes can be formed by different diffraction optical elements and polarization optical elements. This paper proposes a model including a micromirror array and a variable retarder array for forming freeform illumination mode and polarization mode. They can be achieved by controlling the retardations of the variable retarders and two-dimensional tilt angles of the micromirrors. The principles of the model are analyzed, and some equations are acquired. Circular illumination mode, tangential polarization modes have been obtained in the simulation experiments. The simulation results show the model is feasible for the 193 nm immersion lithography machine.

In order to produce various kind of circuit pattern in short-term cycle, mask-less exposure using DMD(digital mirror device)-mask is useful. Although not only fine resolution but also large DOF(depth of focus) can be obtained by using PSM(phase shifting mask), there exists forbidden pitch region for PSM. While the pattern pitch of PSM becomes fine, it cannot be resolved at a certain pitch and it will be resolved again at a finer pattern pitch. This un-resolvable region is called forbidden pitch region. It has been time consuming to predict this region by numerical calculation. Applying PSM to various fields, we should predict the region simply. In this paper, we derive analytical equations which give the optimal NA(Numerical Aperture) and finest resolution and also reveal forbidden region. In addition, we confirm the validity of analytical equation by numerical calculation using PROLITH^TM. This result will be useful to apply PSM in practice.

One key technology in mass microchip-production is an optical projection system (wafer stepper) for deep UV photolithography. Modern wafer stepper-optics featuring sub-200nm resolution, consist of 20 to 25 glass elements with a weight of up to 1000 kg including mechanical parts. After the careful glass element-manufacturing, the optical performance of the system is highly influenced by the precise mechanical alignment of all individual lens elements. The imaging quality of such systems is extremely sensitive to alignment errors as they may severely degrade the imaging quality. Therefore, the optical design of a stepper optic has tight tolerances for the alignment in the sub-μm and arc second range. We will present a high resolution optical measurement system that performs non-contact measurements of centering errors of each surface in an assembled optics with a measurement accuracy of 0.1 μm, and it determines the air gap-distances and lens center-thicknesses with a measurement accuracy of 1.0 μm.

As optical lithography continues to produce ever smaller features on a chip, the industry imposes tighter quality parameters on the optical components used in a lithographic step and scan system. Residual linear birefringence is one such parameter. Currently, optical component suppliers use the Exicor birefringence measurement systems that we have developed to measure photomask blanks and lens blanks to ensure their quality. In this paper, we report a new model of Exicor birefringence measurement system that is specifically designed for measuring lenses. Unlike lens blanks that have flat surfaces, lenses have curved surfaces that refract the measuring light beam to different angles. In this new model of birefringence measurement system, we combine motion control of the light source module, the detector module and the lens under test to achieve accurate measurement of residual birefringence of a lens at different incident angles.

Since flare-related CD variation was observed in some 40-nm test chips, we evaluated the flare level of an ArF immersion scanner by the Kirk method. We found that the tool flare for a 1.3-μm pad was more than 5% and the short-range flare (scattering range < 10 μm) was quite large when the optics were degraded. Optics maintenance reduced the tool flare to about 2%. An evaluation of the impact of short-range flare on the space CDs of 40-nm logic devices revealed it to be quite large. The point spread function for flare was determined from measured flare data, and the flare density was calculated for various patterns. A simulation analysis showed that the measured CD error was closely related to flare density. Since the impact of a change in dose on space CD is nonlinear, the impact of a change in flare is also nonlinear. Simulations using tool flare and flare density can predict most of the CD error. In the active layer of 40-nm logic devices, the flare density is generally in the range of 40-70% for critical space patterns. Varying the dose control pattern from small-area L/S (< 5 μm square) to large-area L/S (50 μm square) should reduce the impact of flare on space CD. Patterns with a medium flare density are preferable for dose control.

To overcome the accuracy limitation due to the aberration of reference wavefront in the interferometer testing, the point diffraction interferometer (PDI) uses the pinhole to create an ideal diffraction sphere wavefront as the reference wavefront. Because the perfect pinhole is hard to manufacture, then the imperfect pinhole will cause the wavefront errors which will influence the test accuracy. In this paper we use the absolute testing method to test the wave front of the pinhole. Then the testing accuracy of point diffraction interferometer can be improved by subtracting the error of the pinhole. In this paper a Phase-shifting point diffraction interferometer system is designed to testing the pinhole. We use three pinholes to test each other. According the algorithm of the absolute testing method, we can calculate the wavefront error of the pinhole. Then the testing accuracy of point diffraction interferometer can be improved by subtracting the error of the pinhole.

An illuminator with a micro scanning slit array for NA 0.75 lithography system has been proposed in this paper. In this illuminator, the beam is shaped by a diffractive optical element (DOE), a zoom and axicon lenses. The beam is homogenized by a micro intergrator rod array. The micro scanning slit array is used to substitute for the traditional internal rema. A micro lens array and a condenser image the micro scanning slit array onto the mask. This illuminator needs no illumination lens group and reduces the effect of the vibration introduced by the internal rema. The illuminator is designed and simulated. The result shows that the illuminating field on the mask has good uniformity and trapezoidal distribution along the scanning direction. The feasibility of the illuminator is verified.

The zero expansion glass ceramic ZERODUR^® is a well-established material in microlithography in critical components as wafer- and reticle-stages, mirrors and frames in the stepper positioning and alignment system. The very low coefficient of thermal expansion (CTE) and its extremely high CTE homogeneity are key properties to achieve the tight overlay requirements of advanced lithography processes. SCHOTT is continuously improving critical material properties of ZERODUR^® essential for microlithography applications according to a roadmap driven by the ever tighter material specifications broken down from the customer roadmaps. This paper will present the SCHOTT Roadmap for ZERODUR^® material property development. In the recent years SCHOTT established a physical model based on structural relaxation to describe the coefficient of thermal expansion’s temperature dependence. The model is successfully applied for the new expansion grade ZERODUR^® TAILORED introduced to the market in 2012. ZERODUR^® TAILORED delivers the lowest thermal expansion of ZERODUR^® products at microlithography tool application temperature allowing for higher thermal stability for tighter overlay control in IC production. Data will be reported demonstrating the unique CTE homogeneity of ZERODUR^® and its very high reproducibility, a necessary precondition for serial production for microlithography equipment components. New data on the bending strength of ZERODUR^® proves its capability to withstand much higher mechanical loads than previously reported. Utilizing a three parameter Weibull distribution it is possible to derive minimum strength values for a given ZERODUR^® surface treatment. Consequently the statistical uncertainties of the earlier approach based on a two parameter Weibull distribution have been eliminated. Mechanical fatigue due to stress corrosion was included in a straightforward way. The derived formulae allows calculating life time of ZERODUR^® components for a given stress load or the allowable maximum stress for a minimum required life time.

Current state-of-the-art optical lithography scanners using 193nm wavelength lasers and numerical apertures of 1.35 have reached fundamental printing limits. Yet, consumer demands and device trends continue to drive smaller feature sizes, and most IC manufacturers have already navigated beyond the lithographic printing limits by turning to double patterning techniques.¹ Requiring an extra lithography step for these techniques, it is essential to keep costs down by e.g. increasing wafer throughput. Currently, leading edge immersion scanners consistently produce over 190 wafers per hour (wph). However, to keep decreasing the cost per transistor, higher throughputs of 250 wph are key targets for the year 2013². Amongst others, higher throughput can be acquired by increasing acceleration of the positioning stages. One of the constraining technologies is the current mask or reticle clamping concept due to its friction based acceleration. While current reticle accelerations amount to 150 m/s², some research³ has already been performed to reticle stage accelerations of 400 m/s². In this paper, a novel reticle clamping concept is presented. The concept is shown to be suitable for accelerations larger than 400 m/s² entirely eliminating reticle slip, whilst meeting specifications for clamping induced error with a pattern deformation of < 0.12 nm on wafer stage level (WS) and comprising high clamp stiffness.