Design level variability analysis and parametric yield improvement methodology

Reinhard März; Martin Keck

doi:10.1117/12.916153

14 March 2012 Design level variability analysis and parametric yield improvement methodology

Reinhard März, Martin Keck

Proceedings Volume 8327, Design for Manufacturability through Design-Process Integration VI; 83270H (2012) https://doi.org/10.1117/12.916153
Event: SPIE Advanced Lithography, 2012, San Jose, California, United States

Abstract

With the transition to the 32/28 nm platform parameter variations of device and circuit parameters are becoming increasingly important for performance, reliability and yield. Based on a sensitivity analysis, the paper compares the impact of lithography and CMP on circuit parameter variations. Coupling capacitances that can be described by geometrical parameters such as line width and thickness impact signal delay, crosstalk noise and power consumption. Variations of these capacitances thus contribute significantly to parametric yield loss. Based on field solver simulations the most critical devices and interconnections can be identified, providing valuable input during the chip design cycle.

Citation Download Citation

Reinhard März and Martin Keck "Design level variability analysis and parametric yield improvement methodology", Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270H (14 March 2012); https://doi.org/10.1117/12.916153

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