Low-power integration of on-chip nanophotonic interconnect for high-performance optoelectrical IC

Duo Ding; David Z. Pan

doi:10.1117/12.913886

2 February 2012 Low-power integration of on-chip nanophotonic interconnect for high-performance optoelectrical IC

Duo Ding, David Z. Pan

Author Affiliations +

Proceedings Volume 8267, Optoelectronic Interconnects XII; 82670Z (2012) https://doi.org/10.1117/12.913886
Event: SPIE OPTO, 2012, San Francisco, California, United States

Abstract

In this manuscript we study the potentials of nanophotonics on-chip integration and propose a set of automation methodologies to construct low power on-chip interconnect with flexible geometry shapes. We show that with such techniques, a systematic design aid environment can be developed to generate optimized integration configurations meanwhile honoring complex sets of photonic device constraints. Due to their unique characteristics, not only do these techniques benefit the optimization of on-chip photonic networks, but also they can be efficiently applied to build low-power high-throughput application specific ICs with opto-electrical interconnection.

Citation Download Citation

Duo Ding and David Z. Pan "Low-power integration of on-chip nanophotonic interconnect for high-performance optoelectrical IC", Proc. SPIE 8267, Optoelectronic Interconnects XII, 82670Z (2 February 2012); https://doi.org/10.1117/12.913886

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