Low-power and high-speed SerDes with new dynamic latch and flip-flop for optical interconnect in 180 nm CMOS technology

Jamshid Sangirov; Ikechi Augustine Ukaegbu; Tae-Woo Lee; Mu Hee Cho; Hyo-Hoon Park

doi:10.1117/12.876237

17 January 2011 Low-power and high-speed SerDes with new dynamic latch and flip-flop for optical interconnect in 180 nm CMOS technology

Jamshid Sangirov, Ikechi Augustine Ukaegbu, Tae-Woo Lee, Mu Hee Cho, Hyo-Hoon Park

Author Affiliations +

Proceedings Volume 7944, Optoelectronic Interconnects and Component Integration XI; 79440V (2011) https://doi.org/10.1117/12.876237
Event: SPIE OPTO, 2011, San Francisco, California, United States

Abstract

We propose a new dynamic D-latch for low-power high-speed SerDes in chip-to-chip optical interconnect. The overall SerDes circuit uses 3.6 times less number of transistors, with smaller SerDes occupying 50% less area, compared to the previous works. The SerDes operates up to 10 Gbps data rate, and the power consumption is 49.3 mW at 1.8 V, which is 30 % less power.

Citation Download Citation

Jamshid Sangirov, Ikechi Augustine Ukaegbu, Tae-Woo Lee, Mu Hee Cho, and Hyo-Hoon Park "Low-power and high-speed SerDes with new dynamic latch and flip-flop for optical interconnect in 180 nm CMOS technology", Proc. SPIE 7944, Optoelectronic Interconnects and Component Integration XI, 79440V (17 January 2011); https://doi.org/10.1117/12.876237

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