Process-induced bias: a study of resist design, device node, illumination conditions, and process implications

Michael Carcasi; Steven Scheer; Carlos Fonseca; Tsuyoshi Shibata; Hitoshi Kosugi; Yoshihiro Kondo; Takashi Saito

doi:10.1117/12.814395

1 April 2009 Process-induced bias: a study of resist design, device node, illumination conditions, and process implications

Michael Carcasi, Steven Scheer, Carlos Fonseca, Tsuyoshi Shibata, Hitoshi Kosugi, Yoshihiro Kondo, Takashi Saito

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Proceedings Volume 7273, Advances in Resist Materials and Processing Technology XXVI; 72730N (2009) https://doi.org/10.1117/12.814395
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

Critical dimension uniformity (CDU) has both across field and across wafer components. CD error generated by across wafer etching non-uniformity and other process variations can have a significant impact on CDU. To correct these across wafer systematic variations, compensation by exposure dose and/or post exposure bake (PEB) temperature have been proposed. These compensation strategies often focus on a specific structure without evaluating how process compensation impacts the CDU of all structures to be printed in a given design. In one previous study limited to a single resist and minimal coater/developer and scanner variations, the authors evaluated the relative merits of across wafer dose and PEB temperature compensation on the process induced CD bias and CDU. For the process studied, it was found that using PEB temperature to control CD across wafer was preferable to using dose compensation. In another previous study, the impact of resist design was explored to understand how resist design, as well as coater/developer and scanner processing, impact process induced bias (PIB). The previous PIB studies were limited to a single illumination case and explore the effect of PIB on only L/S structures. It is the goal of this work to understand additionally how illumination design and mask design, as well as resist design and coater/developer and scanner processing, impact process induced bias (PIB)/OPC integrity.

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Michael Carcasi, Steven Scheer, Carlos Fonseca, Tsuyoshi Shibata, Hitoshi Kosugi, Yoshihiro Kondo, and Takashi Saito "Process-induced bias: a study of resist design, device node, illumination conditions, and process implications", Proc. SPIE 7273, Advances in Resist Materials and Processing Technology XXVI, 72730N (1 April 2009); https://doi.org/10.1117/12.814395

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KEYWORDS

Diffusion

Photoresist processing

Fiber optic illuminators

Semiconducting wafers

Nanoimprint lithography

Optical proximity correction

Critical dimension metrology

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