High-performance bridge-style full adder structure

Omid Kavehei; Said F. Al-Sarawi; Derek Abbott; Keivan Navi

doi:10.1117/12.813924

30 December 2008 High-performance bridge-style full adder structure

Omid Kavehei, Said F. Al-Sarawi, Derek Abbott, Keivan Navi

Proceedings Volume 7268, Smart Structures, Devices, and Systems IV; 72680D (2008) https://doi.org/10.1117/12.813924
Event: SPIE Smart Materials, Nano- and Micro-Smart Systems, 2008, Melbourne, Australia

Abstract

Adders are the core element in arithmetic circuits like subtracters, multipliers, and dividers. Optimization of adders can be achieved at device, circuit, architectural, and algorithmic levels. In this paper we present a new optimize full adder circuit structure that provides an improved performance compared to standard and mirror types adder structures. The performance of this adder in terms of power, delay, energy, and yield are investigated. This paper also proposes a novel simulation setup for full adder cells that is suitable for analyzing full adder cells at the high frequency. The simulation results of this structure will take into account the process variations for a 90 nm CMOS process and present results based on post-layout simulation using Cadence and Synopsys tools.

Citation Download Citation

Omid Kavehei, Said F. Al-Sarawi, Derek Abbott, and Keivan Navi "High-performance bridge-style full adder structure", Proc. SPIE 7268, Smart Structures, Devices, and Systems IV, 72680D (30 December 2008); https://doi.org/10.1117/12.813924

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