An integrated lithography concept with application on 45-nm ½ pitch flash memory devices

Mircea Dusa; Andre Engelen; Jo Finders

doi:10.1117/12.661164

21 March 2006 An integrated lithography concept with application on 45-nm ½ pitch flash memory devices

Mircea Dusa, Andre Engelen, Jo Finders

Proceedings Volume 6154, Optical Microlithography XIX; 61540L (2006) https://doi.org/10.1117/12.661164
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States

Abstract

It is well accepted to judge imaging capability of an exposure tool primarily on printing equal line-spaces, at a minimum ½ pitch. Further on, combining line-space minimum ½ pitches with scanner maximum NA, defines the process k₁. From a lithographer viewpoint, flash memory device is the perfect candidate to achieve lowest k₁ lithography for a given NA. This is justified by flash layout specific, with regular and relative simple 1-D topology of the critical layers that look like line-space gratings. In reality, flash layout presents a subtle topology and cannot be considered a simple 1-D line-space problem. Uniqueness to flash layout is the array-end zones, where pattern regularity is broken up by features with dimensions and separation of n x ½ pitch, where n is an integer number that we used in this work to manipulate litho process latitudes. Integrated lithography concept seeks to tweak flash pattern details and tune it with scanner control parameters. We introduce feature-center placement through focus and dose as the metric to characterize a cross-coupling phenomena occurring between adjacent features located at array-end of typical flash poly wordline layer. We comparedthe metric behavior with usual litho process window parameters and identified interactions with scanner CDU control parameters. We show how feature-center placement errors are direct functions of optical and physical characteristics of mask materials, attenuated PSM or binary, and of layout array-end topology. Imaging at extreme low-k₁, effects from layout specifics and mask materials are best characterized by full vector, rigorous EM simulation, instead of scalar approach, typically used for OPC treatment. Predicted CDU performance of 1.2NA scanner, based on integrated lithography concept, matched very well the experimental results in printing 45nm ½ pitch flash wordline layer. Results show that 1.2NA scanner, operating at 0.28 k₁ could be an effective lithography solution for 45nm flash designs.

Citation Download Citation

Mircea Dusa, Andre Engelen, and Jo Finders "An integrated lithography concept with application on 45-nm ½ pitch flash memory devices", Proc. SPIE 6154, Optical Microlithography XIX, 61540L (21 March 2006); https://doi.org/10.1117/12.661164

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