Three-dimensional micro-optical architecture for chip-level optical interconnects

Dennis W. Prather; Sriram Venkatraraman; Marion R. LeCompte; Harry E. Bates Jr.; Fouad E. Kiamilev

doi:10.1117/12.428031

30 May 2001 Three-dimensional micro-optical architecture for chip-level optical interconnects

Dennis W. Prather, Sriram Venkatraraman, Marion R. LeCompte, Harry E. Bates Jr., Fouad E. Kiamilev

Author Affiliations +

Proceedings Volume 4292, Optoelectronic Interconnects VIII; (2001) https://doi.org/10.1117/12.428031
Event: Symposium on Integrated Optics, 2001, San Jose, CA, United States

Abstract

As processor speeds enter the Gigahertz regime, the disparity between processing time and memory access time plays an increasingly important role in the overall limitation of processor performance. Furthermore, as the components continue to shrink in size, the limitations in interconnect density and bandwidth serve to exacerbate communication bottlenecks. To address these issues, we propose a 3D architecture based on through-wafer vertical optical interconnects. Our system is monolithically fabricated on a single host substrate and preserves the VLSI-scale of integration by using meso-scopic diffractive optical elements for beam fan-out and signal distribution at the chip level.

Citation Download Citation

Dennis W. Prather, Sriram Venkatraraman, Marion R. LeCompte, Harry E. Bates Jr., and Fouad E. Kiamilev "Three-dimensional micro-optical architecture for chip-level optical interconnects", Proc. SPIE 4292, Optoelectronic Interconnects VIII, (30 May 2001); https://doi.org/10.1117/12.428031

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