Paper
23 October 2000 Novel algorithm for hot-carrier lifetime projection on thick gate PMOSFETs fabricated by 0.18-um CMOS technology
Bin Bin Jie, Indrajit Manna, Xu Zeng, Qiang Guo, Keng Foo Lo
Author Affiliations +
Proceedings Volume 4229, Microelectronic Yield, Reliability, and Advanced Packaging; (2000) https://doi.org/10.1117/12.404884
Event: International Symposium on Microelectronics and Assembly, 2000, Singapore, Singapore
Abstract
It is critical how to project hot-carrier lifetime form wafer level hot-carrier injection (HCl) test data, due to the limited stress time. It is well known that both oxide charge formation and interface trap generation affect the degradation of thick gate PMOSFETs fabricated by 0.18 micrometers technology. Based on it, a new fitting mode and the corresponding fitting algorithm were proposed. Form only one experimental curve of any degradation versus stress time under any HCl stress condition, the corresponding fitting curve can be obtained using this model. Form the fitting curve, the hot-carrier lifetime under the corresponding stress condition can be extracted. It is shown here that the model is quite accurate. This algorithm is quite robust to extract HCl lifetime as well.
© (2000) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Bin Bin Jie, Indrajit Manna, Xu Zeng, Qiang Guo, and Keng Foo Lo "Novel algorithm for hot-carrier lifetime projection on thick gate PMOSFETs fabricated by 0.18-um CMOS technology", Proc. SPIE 4229, Microelectronic Yield, Reliability, and Advanced Packaging, (23 October 2000); https://doi.org/10.1117/12.404884
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KEYWORDS
Oxides

Human-computer interaction

Interfaces

CMOS technology

Electrons

Semiconducting wafers

Transistors

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