Analysis of serious bit-line failure on 0.19-um 64M DRAM with STI technology

Chung Lee; Chih-Tung Tang

doi:10.1117/12.404865

23 October 2000 Analysis of serious bit-line failure on 0.19-um 64M DRAM with STI technology

Chung Lee, Chih-Tung Tang

Proceedings Volume 4229, Microelectronic Yield, Reliability, and Advanced Packaging; (2000) https://doi.org/10.1117/12.404865
Event: International Symposium on Microelectronics and Assembly, 2000, Singapore, Singapore

Abstract

When 0.19um 64M DRAM was been developing that suffered very serious bit line failure. Because it is the first product with shallow trench isolation (STI) technology in VIS, obviously some previous FA experiences in LOCOS is not applicable to this case. After took much effort, finally, cross section/plane view TEM and Wright etching analysis shown there were two root causes. 1) Stress induced dislocation in silicon is the major problem witch always occurs at special layout and induced most of the bit line fail (especially long bit line fail). 2) Poly plug residue from improper IPO1 CMP induced bit line fail.

Citation Download Citation

Chung Lee and Chih-Tung Tang "Analysis of serious bit-line failure on 0.19-um 64M DRAM with STI technology", Proc. SPIE 4229, Microelectronic Yield, Reliability, and Advanced Packaging, (23 October 2000); https://doi.org/10.1117/12.404865

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