PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.
An integrated system for visual pattern processing was proposed in this paper for implemented with CMOS technology. It consists of three parts: Variable Sensitivity Photo Detectors, control circuit, and parallel network. A 256 X 256 pixels array of 3-bits resolution is designed into the system chip for pattern recognition. In order to testing the design result, it was simulated with Spice model parameters of 1.2 micrometers CMOS process.
Donghui Guo,Suntao Wu,Gerard Parr,Ruitang Liu, andBoxi Wu
"System integration for visual pattern processing based on CMOS technology", Proc. SPIE 4077, International Conference on Sensors and Control Techniques (ICSC 2000), (9 May 2000); https://doi.org/10.1117/12.385574
ACCESS THE FULL ARTICLE
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.
The alert did not successfully save. Please try again later.
Donghui Guo, Suntao Wu, Gerard Parr, Ruitang Liu, Boxi Wu, "System integration for visual pattern processing based on CMOS technology," Proc. SPIE 4077, International Conference on Sensors and Control Techniques (ICSC 2000), (9 May 2000); https://doi.org/10.1117/12.385574