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According to the classical calculation of overlay margin as 1/4 design rule, the overlay control requirement for sub-0.15 micrometer design rule device is nominally below 40 nm. To meet this demand, it is necessary that one should analyze every part in global alignment and overlay measurement procedure, then factor out the parameter that is known to affect overlay control, and correct it as much as possible. One of the major causes degrading overlay budget seems to be the nonoptimized wafer sampling method. Compensated but undercorrected overlay errors usually fitted as linear terms can be amplified due to improper sampling method e.g. asymmetric one. In this paper, we have investigated the possible causes that yield global alignment noise and the sampling method dependency of global alignment repeatability and overlay model calculations. The achievement of better alignment repeatability is critical for improving not only in- wafer overlay but wafer-to-wafer overlay control. It is thus evident that overlay control can be improved by reducing alignment noises or by optimizing sampling method. Global alignment repeatability and its results are significantly affected by which chips in a wafer map are selected as global alignment purpose. This result can be understood as noise margin is different for each sampling plan and there exists an optimal sampling method. We tested several sampling methods that belong to symmetric group (translation, inversion, rotation symmetric), which are known to show better noise margin. The criteria to select the best sampling method were residual and linear term reproducibility which are significantly affected by raw data noise. The raw data variations include stage position errors and process induced alignment signal abnormality. We found among the candidates the optimal sampling method which leaves the least residual and shows as good repeatability as full chip measurement. Similar results could be obtained for overlay sampling method.
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