Sub-0.25-um defect analysis on 200-mm semiconductor wafers

Kenton D. Childs; Dennis F. Paul; Stephen P. Clough

doi:10.1117/12.240141

21 May 1996 Sub-0.25-um defect analysis on 200-mm semiconductor wafers

Kenton D. Childs, Dennis F. Paul, Stephen P. Clough

Proceedings Volume 2725, Metrology, Inspection, and Process Control for Microlithography X; (1996) https://doi.org/10.1117/12.240141
Event: SPIE's 1996 International Symposium on Microlithography, 1996, Santa Clara, CA, United States

Abstract

The semiconductor industry has demonstrated the need for off-line, capital intensive analytical instruments to increase semiconductor yields through quick and accurate analysis of detected defects. Leading edge semiconductor devices currently employ 0.35 micron design rule features and this is expected to shrink to 0.25 micron by 1998 and 0.18 micron by 2001. A rule-of-thumb estimate for satisfactory device yield requires that defect detection and identification is necessary at one third of the design rule. Thus current leading edge devices require defect detection and identification for defects less than 0.12 micron, decreasing to 0.08 micron in 1998 and 0.06 micron in 2001. The primary analytical tool for whole wafer sub- micron defect analysis is generically called a defect review tool (DRT). A DRT relies on energy dispersive x-ray (EDX) analysis for elemental identification. EDX provides superior analytical results for defects greater than 1.0 micron in size and can be utilized with decreasing efficiency and accuracy for sub-micron defects. EDX has great difficulty with elemental analysis of defects less than 0.25 micron, twice the current leading edge requirement. Auger electron spectroscopy (AES) has been demonstrated to be a superior elemental analysis tool for very small analytical volumes. AES has not been extensively used for wafer level defect analysis because of limitations due to the required ultra-high vacuum (UHV) sample handling and the lack of suitable defect navigation software. The development of a 200 mm UHV wafer handling system and navigation software permits the effective utilization of AES in a commercial DRT. This newly developed system, the SMART-200, is discussed in detail.

Citation Download Citation

Kenton D. Childs, Dennis F. Paul, and Stephen P. Clough "Sub-0.25-um defect analysis on 200-mm semiconductor wafers", Proc. SPIE 2725, Metrology, Inspection, and Process Control for Microlithography X, (21 May 1996); https://doi.org/10.1117/12.240141

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