Solving production process challenges with wafer-level reliability techniques

J. Shideler; Joseph Reedholm; C.B. Chuck Yarling

doi:10.1117/12.221447

22 September 1995 Solving production process challenges with wafer-level reliability techniques

J. Shideler, Joseph Reedholm, C.B. Chuck Yarling

Proceedings Volume 2635, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis; (1995) https://doi.org/10.1117/12.221447
Event: Microelectronic Manufacturing '95, 1995, Austin, TX, United States

Abstract

Many major semiconductor fabs are beginning to implement wafer-level reliability (WLR) as a means to improve both quality and yield of their product. Presently available WLR test structures provide a method for the reliability engineer to monitor the reliability of advanced state- of-the-art devices manufactured from CMOS, Bipolar, and BiCMOS technologies. However, these test structures also provide statistical parameters resulting from 'integrated', i.e., multiple processes. This paper examines how in-line testing of presently available WLR test structures can enable the process engineer to uniquely examine various process control parameters. Results in the form of tables and control charts show that implementation of WLR in the manufacturing area provide data useful to process, equipment, and reliability engineers.

Citation Download Citation

J. Shideler, Joseph Reedholm, and C.B. Chuck Yarling "Solving production process challenges with wafer-level reliability techniques", Proc. SPIE 2635, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis, (22 September 1995); https://doi.org/10.1117/12.221447

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