DSP-based hardware for real-time video coding

Luis A. S. V. de Sa; Vitor Mendes Silva; Luis J. de la Cruz; Sergio Faria; Pedro J. Amado; Antonio Navarro; Fernando Lopes; Joao Carlos Silvestre

doi:10.1117/12.58419

30 April 1992 DSP-based hardware for real-time video coding

Luis A. S. V. de Sa, Vitor Mendes Silva, Luis J. de la Cruz, Sergio Faria, Pedro J. Amado, Antonio Navarro, Fernando Lopes, Joao Carlos Silvestre

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Proceedings Volume 1659, Image Processing and Interchange: Implementation and Systems; (1992) https://doi.org/10.1117/12.58419
Event: SPIE/IS&T 1992 Symposium on Electronic Imaging: Science and Technology, 1992, San Jose, CA, United States

Abstract

An important application of digital image processing is the compression of video sequences by one or two orders of magnitude with minor picture quality degradation. In order to achieve this data compression elaborated algorithms are used. They eliminate both spatial and temporal redundancy by using transform, differential, and variable length coding techniques. Two of these algorithms are the CCITT H.261 algorithm for videotelephony and the ISO MPEG algorithm for CD-ROM motion video. The hardware implementation of these algorithms is a formidable task in view of the number of operations (more than 1GFLOPS) that may be necessary. This paper discusses the compression and decompression of real-time video using a multiprocessor system based on digital signal processors. The system is based on the partition of each picture in horizontal strips which are operated by a local processor unit made by the combination of the TMS320C30 signal processor and an A121 discrete cosine transform processor. In the encoder, each strip processor inputs raw data from a video acquisition module through a common parallel video bus and outputs compressed data to a supervisor module through a common serial supervisor bus. In the decoder, the data flows through an inverse path, i.e., the processors receive data from a supervisor module and transmit data to a display module. All operations within the horizontal strips are independent from each other except when motion estimation is used. In this case, the processing elements have to access regions of the picture that are allocated to neighboring processors. The number of processors is related to the frame rate and the resolution of the image.

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Luis A. S. V. de Sa, Vitor Mendes Silva, Luis J. de la Cruz, Sergio Faria, Pedro J. Amado, Antonio Navarro, Fernando Lopes, and Joao Carlos Silvestre "DSP-based hardware for real-time video coding", Proc. SPIE 1659, Image Processing and Interchange: Implementation and Systems, (30 April 1992); https://doi.org/10.1117/12.58419

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