Mask synthesis and writing is the first and the most critical step in chip making, and its quality has a direct impact on the final wafer yield. In the past two decades, the mask industry has been working with EDA vendors and foundry customers to address the challenges arising from feature-scaling, immortalized by Moore’s law and improve the yield while controlling the cost of mask making within check. Great progresses has been made, and currently three trends are the industry’s consensus: curvilinear masks; ML modeling; GPU for model calibration and mask correction. In this talk, the authors will briefly review the history of how different trends converged to the current status, and report some of the current status of Bezier-spline based curvilinear OPC and ILT on CPU and GPU, and the mask correction with embedded e-beam, lithography and etch models, and point some of the remaining challenges that call for the mask industry, software and hardware vendors, to work together to address them for the wide adoption of the new technologies at the most advanced nodes as well as the more mature nodes.
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