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This paper presents a 14-bit column-parallel two-step compact hybrid ADC for low-power digital IRFPA application, with the area and speed performances compromise. The proposed two-step ADC works in two phases: in the first phase, A 7-bit SAR ADC performs the coarse quantization; in the second phase, a 7-bit SS ADC further performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, and the main clock of fine SS ADC can be reduced to 50MHz at the sampling rate of 238 kS/s. More importantly, by sharing analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are reduced consequently. The proposed two-step ADC is designed in 0.18 μm standard CMOS process. The simulation results show that the proposed two-step ADC has a differential nonlinearity of −0.87/+0.43 LSB and an integral nonlinearity of −0.86/+0.71 LSB. The layout of the proposed ADC can be implemented in the pixel pitch less than 10 μm. The conversion time is 4.2 μs, and the power consumption of each column ADC is only 65 μW with a 3.3V power supply. The simulation results indicate the proposed two-step ADC is suitable for low-power digital readout circuits in the small pixel pitch IRFPA.
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