Design of the scheme of clock jitter cache for circuit emulation service over packet

Ge Jiang; Wangsheng Xu

doi:10.1117/12.2679411

16 June 2023 Design of the scheme of clock jitter cache for circuit emulation service over packet

Ge Jiang, Wangsheng Xu

Proceedings Volume 12702, International Conference on Intelligent Systems, Communications, and Computer Networks (ISCCN 2023); 127022R (2023) https://doi.org/10.1117/12.2679411
Event: International Conference on Intelligent Systems, Communications, and Computer Networks (ISCCN 2023), 2023, Changsha, China

Abstract

CEP emulation provides the possibility of transmitting TDM services in packet-switched networks, where jitters in the transmission network causes the time of receiving a packet at the receiving end to vary constantly. In order to improve the performance of circuit emulation switching services, overcome the problems brought by packet networks for circuit emulation switching functions, and achieve a smooth transition of TDM signal transmission, this paper will study the principle and application of packet circuit emulation functions from the perspective of application in the network circuit emulation clock jitters caching technology, and propose a clock jitters caching scheme, whose main function is to absorb the packet reception jitters caused by network delay, and The main function of the clock jitters cache scheme is to absorb packet jitters caused by network delay, and to achieve chaotic reorder and packet loss compensation.

Citation Download Citation

Ge Jiang and Wangsheng Xu "Design of the scheme of clock jitter cache for circuit emulation service over packet", Proc. SPIE 12702, International Conference on Intelligent Systems, Communications, and Computer Networks (ISCCN 2023), 127022R (16 June 2023); https://doi.org/10.1117/12.2679411

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