A study of diffraction-based overlay (DBO) on a 3nm CFET metal layer

Yanli Li; Yayi Wei; Qiang Wu; Xianhe Liu; Qi Wang

doi:10.1117/12.2658167

27 April 2023 A study of diffraction-based overlay (DBO) on a 3nm CFET metal layer

Yanli Li, Yayi Wei, Qiang Wu, Xianhe Liu, Qi Wang

Author Affiliations +

Proceedings Volume 12496, Metrology, Inspection, and Process Control XXXVII; 124962Y (2023) https://doi.org/10.1117/12.2658167
Event: SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States

Conference Poster

Abstract

Two of most important parameters for the integrated circuit manufacturing are linewidth and overlay. The linewidth uniformity is guaranteed by good exposure tooling, photoresist material, photomasks, Optical Proximity Correction (OPC), optimized patterning process, and good metrology. The linewidth metrology utilized the Scanning Electron Microscope (SEM) directly, which accuracy is entirely determined by the equipment. The overlay metrology quality, however, not only depends on the equipment performance, but can also depend on the substrate quality. There are two types of overlay measurement techniques, i.e., the Image Based Overlay (IBO) and the Diffraction Based Overlay (DBO). In this paper, we will focus our study on a 3 nm Complementary FET (CFET) metal layer overlay. The dimensions of a 3 nm logic design can be as small as 20~24 nm for the Fin Pitch (FP) and 36~48 nm for the Contacted Poly Pitch (CPP) and a On Product Overlay (OPO) of 2.5 nm is required. We will report our study on the DBO for the metal to metal overlay under typical 3 nm logic CFET design rules and a proposed film stack.

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Yanli Li, Yayi Wei, Qiang Wu, Xianhe Liu, and Qi Wang "A study of diffraction-based overlay (DBO) on a 3nm CFET metal layer", Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 124962Y (27 April 2023); https://doi.org/10.1117/12.2658167

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