NBTI in SiGe transistors

Gilson Wirth

doi:10.1117/12.2500875

24 January 2019 NBTI in SiGe transistors

Gilson Wirth

Proceedings Volume 11043, Fifth Conference on Sensors, MEMS, and Electro-Optic Systems; 1104311 (2019) https://doi.org/10.1117/12.2500875
Event: Fifth Conference on Sensors, MEMS, and Electro-Optic Systems, 2018, Skukuza, South Africa

Abstract

For advanced technology nodes, device engineering efforts are focused on high mobility designs for performance enhancement, such as channel designs with Ge. Considering reliability, bias temperature instability (BTI) is among the major concerns. It is therefore mandatory to proper understand, characterize and model BTI in these technologies. It has been reported that SiGe pMOSFETs with a buried channel show improved BTI robustness. It was shown that the Si cap thickness plays a significant role on BTI behavior. The threshold voltage shift (ΔVth) of the FET was found to be made up by individual charge trapping events, and thinner Si caps significantly improve the reliability. This behavior is here discussed in the framework of charge trapping model, showing that it is consistent with the assumed parameters, such as the distribution of trap amplitude, and a trap energy distribution that is minimum at the band gap center and maximum close to the valence band. Besides analytical analysis, Monte Carlo simulations are performed, highlighting that the modeling framework is applicable to compact modeling of BTI in nanoscale SiGe MOSFETs.

Citation Download Citation

Gilson Wirth "NBTI in SiGe transistors", Proc. SPIE 11043, Fifth Conference on Sensors, MEMS, and Electro-Optic Systems, 1104311 (24 January 2019); https://doi.org/10.1117/12.2500875

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