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6 July 2018 Monitor and control for the SKA1 CSP Mid.CBF utilizing the Stratix-10 FPGA equipped with HPS
David A. Del Rizzo, Mark A. B. Garstin
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Proceedings Volume 10707, Software and Cyberinfrastructure for Astronomy V; 107071S (2018) https://doi.org/10.1117/12.2309986
Event: SPIE Astronomical Telescopes + Instrumentation, 2018, Austin, Texas, United States
Abstract
We present design considerations and a prototyping progress report for a low-level monitor and control communication system designed to operate on the Stratix-10 System on a Chip (SoC) Field Programmable Gate Array (FPGA) equipped with a Hard Processor System (HPS). The goal of this activity is to allow remote clients to use high level communication protocols (ie. TANGO) to access IP blocks within a Stratix-10 FPGA chip by taking advantage of very low latency communication between HPS and the FPGA fabric, eliminating the need to implement Ethernet protocols within the FPGA logic.
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David A. Del Rizzo and Mark A. B. Garstin "Monitor and control for the SKA1 CSP Mid.CBF utilizing the Stratix-10 FPGA equipped with HPS", Proc. SPIE 10707, Software and Cyberinfrastructure for Astronomy V, 107071S (6 July 2018); https://doi.org/10.1117/12.2309986
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KEYWORDS
Field programmable gate arrays
Prototyping
Control systems
Operating systems
System on a chip
Interfaces
Software development
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