Integrated Optical Pipeline Processor

R. P. Kenan; C. M. Verber

doi:10.1117/12.964027

13 February 1986 Integrated Optical Pipeline Processor

R. P. Kenan, C. M. Verber

Proceedings Volume 0634, Optical and Hybrid Computing; (1986) https://doi.org/10.1117/12.964027
Event: Optical and Hybrid Computing, 1986, Leesburg, United States

Abstract

A pipelined processor is characterized by the use of multiple processors, each programmed to perform a specific part of an overall computing task. The task is typically broken down into segments that are conveniently performed as a unit, but which must be completed before the next segment is started. Such computational units, placed sequentially so as to perform the computing task, comprise the pipeline. Data and input parameters are provided to each computing unit as needed, externally from the system memory or internally from the preceding unit. To help control the flow of data and results, the pipeline is often run synchronously, with one output from each unit occurring each i time units. Units which complete their tasks in less time must wait for the other units to finish. This favors the use of systolic pipelines, as proposed by Kungl.

Citation Download Citation

R. P. Kenan and C. M. Verber "Integrated Optical Pipeline Processor", Proc. SPIE 0634, Optical and Hybrid Computing, (13 February 1986); https://doi.org/10.1117/12.964027

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available